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https://github.com/YosysHQ/yosys
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SigSpec refactoring: using the accessor functions everywhere
This commit is contained in:
Clifford Wolf
parent
16e5ae0b92
commit
4b4048bc5f
62 changed files with 800 additions and 800 deletions
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@ -134,17 +134,17 @@ std::string id(std::string internal_id, bool may_rename = true)
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bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name)
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{
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sig.optimize();
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if (sig.__chunks.size() != 1 || sig.__chunks[0].wire == NULL)
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if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL)
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return false;
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if (reg_wires.count(sig.__chunks[0].wire->name) == 0)
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if (reg_wires.count(sig.chunks()[0].wire->name) == 0)
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return false;
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reg_name = id(sig.__chunks[0].wire->name);
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if (sig.__width != sig.__chunks[0].wire->width) {
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if (sig.__width == 1)
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reg_name += stringf("[%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset);
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reg_name = id(sig.chunks()[0].wire->name);
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if (sig.size() != sig.chunks()[0].wire->width) {
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if (sig.size() == 1)
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reg_name += stringf("[%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset);
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else
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reg_name += stringf("[%d:%d]", sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset + sig.__chunks[0].width - 1,
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sig.__chunks[0].wire->start_offset + sig.__chunks[0].offset);
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reg_name += stringf("[%d:%d]", sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset + sig.chunks()[0].width - 1,
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sig.chunks()[0].wire->start_offset + sig.chunks()[0].offset);
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}
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return true;
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}
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@ -221,12 +221,12 @@ void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false)
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void dump_sigspec(FILE *f, RTLIL::SigSpec &sig)
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{
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if (sig.__chunks.size() == 1) {
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dump_sigchunk(f, sig.__chunks[0]);
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if (sig.chunks().size() == 1) {
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dump_sigchunk(f, sig.chunks()[0]);
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} else {
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fprintf(f, "{ ");
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for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) {
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if (it != sig.__chunks.rbegin())
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for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {
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if (it != sig.chunks().rbegin())
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fprintf(f, ", ");
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dump_sigchunk(f, *it, true);
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}
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@ -300,11 +300,11 @@ std::string cellname(RTLIL::Cell *cell)
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if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections.count("\\Q") > 0)
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{
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RTLIL::SigSpec sig = cell->connections["\\Q"];
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if (sig.__width != 1 || sig.is_fully_const())
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if (sig.size() != 1 || sig.is_fully_const())
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goto no_special_reg_name;
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sig.optimize();
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RTLIL::Wire *wire = sig.__chunks[0].wire;
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RTLIL::Wire *wire = sig.chunks()[0].wire;
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if (wire->name[0] != '\\')
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goto no_special_reg_name;
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@ -318,7 +318,7 @@ std::string cellname(RTLIL::Cell *cell)
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cell_name = cell_name + "_reg";
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if (wire->width != 1)
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cell_name += stringf("[%d]", wire->start_offset + sig.__chunks[0].offset);
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cell_name += stringf("[%d]", wire->start_offset + sig.chunks()[0].offset);
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if (active_module && active_module->count_id(cell_name) > 0)
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goto no_special_reg_name;
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@ -532,7 +532,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
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if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe")
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{
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int width = cell->parameters["\\WIDTH"].as_int();
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int s_width = cell->connections["\\S"].__width;
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int s_width = cell->connections["\\S"].size();
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std::string func_name = cellname(cell);
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fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
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@ -725,7 +725,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
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fprintf(f, ",");
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first_arg = false;
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fprintf(f, "\n%s .%s(", indent.c_str(), id(it->first).c_str());
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if (it->second.__width > 0)
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if (it->second.size() > 0)
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dump_sigspec(f, it->second);
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fprintf(f, ")");
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}
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@ -751,7 +751,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_
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fprintf(f, "%s" "begin\n", indent.c_str());
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for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) {
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if (it->first.__width == 0)
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if (it->first.size() == 0)
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continue;
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fprintf(f, "%s ", indent.c_str());
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dump_sigspec(f, it->first);
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@ -772,7 +772,7 @@ void dump_case_body(FILE *f, std::string indent, RTLIL::CaseRule *cs, bool omit_
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void dump_proc_switch(FILE *f, std::string indent, RTLIL::SwitchRule *sw)
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{
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if (sw->signal.__width == 0) {
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if (sw->signal.size() == 0) {
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fprintf(f, "%s" "begin\n", indent.c_str());
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for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) {
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if ((*it)->compare.size() == 0)
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@ -811,9 +811,9 @@ void case_body_find_regs(RTLIL::CaseRule *cs)
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case_body_find_regs(*it2);
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for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) {
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for (size_t i = 0; i < it->first.__chunks.size(); i++)
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if (it->first.__chunks[i].wire)
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reg_wires.insert(it->first.__chunks[i].wire->name);
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for (size_t i = 0; i < it->first.chunks().size(); i++)
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if (it->first.chunks()[i].wire)
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reg_wires.insert(it->first.chunks()[i].wire->name);
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}
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}
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@ -823,9 +823,9 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r
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case_body_find_regs(&proc->root_case);
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for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++)
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for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
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for (size_t i = 0; i < it2->first.__chunks.size(); i++)
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if (it2->first.__chunks[i].wire)
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reg_wires.insert(it2->first.__chunks[i].wire->name);
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for (size_t i = 0; i < it2->first.chunks().size(); i++)
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if (it2->first.chunks()[i].wire)
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reg_wires.insert(it2->first.chunks()[i].wire->name);
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}
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return;
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}
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@ -876,7 +876,7 @@ void dump_process(FILE *f, std::string indent, RTLIL::Process *proc, bool find_r
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}
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for (auto it = sync->actions.begin(); it != sync->actions.end(); it++) {
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if (it->first.__width == 0)
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if (it->first.size() == 0)
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continue;
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fprintf(f, "%s ", indent.c_str());
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dump_sigspec(f, it->first);
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@ -911,9 +911,9 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
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RTLIL::SigSpec sig = cell->connections["\\Q"];
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sig.optimize();
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if (sig.__chunks.size() == 1 && sig.__chunks[0].wire)
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for (int i = 0; i < sig.__chunks[0].width; i++)
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reg_bits.insert(std::pair<RTLIL::Wire*,int>(sig.__chunks[0].wire, sig.__chunks[0].offset+i));
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if (sig.chunks().size() == 1 && sig.chunks()[0].wire)
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for (int i = 0; i < sig.chunks()[0].width; i++)
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reg_bits.insert(std::pair<RTLIL::Wire*,int>(sig.chunks()[0].wire, sig.chunks()[0].offset+i));
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}
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for (auto &it : module->wires)
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{
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