mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-29 01:18:46 +00:00
Code Activity

SigSpec refactoring: using the accessor functions everywhere

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 20:15:14 +02:00
parent 16e5ae0b92
commit 4b4048bc5f
62 changed files with 800 additions and 800 deletions
Download patch file Download diff file Expand all files Collapse all files

24
backends/intersynth/intersynth.cc
View file

@ -30,23 +30,23 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
{
sig.optimize();
if (sig.__chunks.size() != 1)
if (sig.chunks().size() != 1)
error:
log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.__width, sig.__width, sig.__width));
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
if (sig.__chunks[0].wire == NULL) {
celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.__width, sig.__width, sig.__width));
constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.__width, sig.__chunks[0].data.as_int(),
sig.__width, sig.__width, sig.__chunks[0].data.as_int(), sig.__chunks[0].data.as_int()));
return stringf("CONST_%d_0x%x", sig.__width, sig.__chunks[0].data.as_int());
if (sig.chunks()[0].wire == NULL) {
celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.size(), sig.size(), sig.size()));
constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.size(), sig.chunks()[0].data.as_int(),
sig.size(), sig.size(), sig.chunks()[0].data.as_int(), sig.chunks()[0].data.as_int()));
return stringf("CONST_%d_0x%x", sig.size(), sig.chunks()[0].data.as_int());
}
if (sig.__chunks[0].offset != 0 || sig.__width != sig.__chunks[0].wire->width)
if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width)
goto error;
return RTLIL::unescape_id(sig.__chunks[0].wire->name);
return RTLIL::unescape_id(sig.chunks()[0].wire->name);
}
struct IntersynthBackend : public Backend {
@ -177,9 +177,9 @@ struct IntersynthBackend : public Backend {
node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
for (auto &port : cell->connections) {
RTLIL::SigSpec sig = sigmap(port.second);
if (sig.__width != 0) {
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.__width, sig.__width, sig.__width));
celltype_code += stringf(" b%d %s%s", sig.__width, ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
if (sig.size() != 0) {
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
celltype_code += stringf(" b%d %s%s", sig.size(), ct.cell_output(cell->type, port.first) ? "*" : "", RTLIL::id2cstr(port.first));
node_code += stringf(" %s %s", RTLIL::id2cstr(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str());
}
}