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Tidy/reflow some things

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Krystine Sherwin 2023-08-03 10:23:39 +12:00
parent 2c75b103d6
commit 4b40372446
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10 changed files with 433 additions and 443 deletions

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@ -43,15 +43,15 @@ directories:
simulation results of the synthesized design to the original sources to
logic equivalence checking of entire CPU cores.
The top-level Makefile includes frontends/\*/Makefile.inc,
passes/\*/Makefile.inc and backends/\*/Makefile.inc. So when extending Yosys it
is enough to create a new directory in frontends/, passes/ or backends/ with
your sources and a Makefile.inc. The Yosys kernel automatically detects all
commands linked with Yosys. So it is not needed to add additional commands to a
central list of commands.
The top-level Makefile includes ``frontends/*/Makefile.inc``,
``passes/*/Makefile.inc`` and ``backends/*/Makefile.inc``. So when extending
Yosys it is enough to create a new directory in ``frontends/``, ``passes/`` or
``backends/`` with your sources and a ``Makefile.inc``. The Yosys kernel
automatically detects all commands linked with Yosys. So it is not needed to add
additional commands to a central list of commands.
Good starting points for reading example source code to learn how to write
passes are passes/opt/opt_rmdff.cc and passes/opt/opt_merge.cc.
passes are ``passes/opt/opt_rmdff.cc`` and ``passes/opt/opt_merge.cc``.
See the top-level README file for a quick Getting Started guide and build
instructions. The Yosys build is based solely on Makefiles.

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@ -99,14 +99,14 @@ Selections intro
~~~~~~~~~~~~~~~~
Most commands can operate not only on the entire design but also specifically on
selected parts of the design. For example the command dump will print all
selected objects in the current design while dump foobar will only print the
module foobar and dump \* will print the entire design regardless of the current
selection.
selected parts of the design. For example the command ``dump`` will print all
selected objects in the current design while ``dump foobar`` will only print the
module ``foobar`` and ``dump *`` will print the entire design regardless of the
current selection.
.. code:: yoscrypt
dump */t:$add %x:+[A] \*/w:\* %i
dump */t:$add %x:+[A] */w:* %i
The selection mechanism is very powerful. For example the command above will
print all wires that are connected to the ``\A`` port of a ``$add`` cell.