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Tidy/reflow some things
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10 changed files with 433 additions and 443 deletions
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@ -43,15 +43,15 @@ directories:
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simulation results of the synthesized design to the original sources to
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logic equivalence checking of entire CPU cores.
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The top-level Makefile includes frontends/\*/Makefile.inc,
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passes/\*/Makefile.inc and backends/\*/Makefile.inc. So when extending Yosys it
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is enough to create a new directory in frontends/, passes/ or backends/ with
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your sources and a Makefile.inc. The Yosys kernel automatically detects all
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commands linked with Yosys. So it is not needed to add additional commands to a
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central list of commands.
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The top-level Makefile includes ``frontends/*/Makefile.inc``,
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``passes/*/Makefile.inc`` and ``backends/*/Makefile.inc``. So when extending
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Yosys it is enough to create a new directory in ``frontends/``, ``passes/`` or
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``backends/`` with your sources and a ``Makefile.inc``. The Yosys kernel
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automatically detects all commands linked with Yosys. So it is not needed to add
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additional commands to a central list of commands.
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Good starting points for reading example source code to learn how to write
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passes are passes/opt/opt_rmdff.cc and passes/opt/opt_merge.cc.
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passes are ``passes/opt/opt_rmdff.cc`` and ``passes/opt/opt_merge.cc``.
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See the top-level README file for a quick Getting Started guide and build
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instructions. The Yosys build is based solely on Makefiles.
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@ -99,14 +99,14 @@ Selections intro
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~~~~~~~~~~~~~~~~
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Most commands can operate not only on the entire design but also specifically on
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selected parts of the design. For example the command dump will print all
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selected objects in the current design while dump foobar will only print the
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module foobar and dump \* will print the entire design regardless of the current
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selection.
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selected parts of the design. For example the command ``dump`` will print all
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selected objects in the current design while ``dump foobar`` will only print the
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module ``foobar`` and ``dump *`` will print the entire design regardless of the
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current selection.
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.. code:: yoscrypt
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dump */t:$add %x:+[A] \*/w:\* %i
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dump */t:$add %x:+[A] */w:* %i
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The selection mechanism is very powerful. For example the command above will
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print all wires that are connected to the ``\A`` port of a ``$add`` cell.
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