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https://github.com/YosysHQ/yosys
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cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
This commit is contained in:
Emil J. Tywoniak
parent
960bca0196
commit
4b29f64142
7 changed files with 383 additions and 64 deletions
195
kernel/cost.cc
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195
kernel/cost.cc
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@ -0,0 +1,195 @@
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#include "kernel/cost.h"
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USING_YOSYS_NAMESPACE
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unsigned int CellCosts::get(RTLIL::Module *mod)
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{
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if (mod_cost_cache_.count(mod->name))
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return mod_cost_cache_.at(mod->name);
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unsigned int module_cost = 1;
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for (auto c : mod->cells()) {
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unsigned int new_cost = module_cost + get(c);
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module_cost = new_cost >= module_cost ? new_cost : INT_MAX;
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}
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mod_cost_cache_[mod->name] = module_cost;
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return module_cost;
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}
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static unsigned int y_coef(RTLIL::IdString type)
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{
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if (
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// equality
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type.in(ID($bweqx), ID($nex), ID($eqx)) ||
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// basic logic
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type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($not)) ||
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// mux
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type.in(ID($bwmux), ID($mux)) ||
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// others
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type == ID($tribuf)) {
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return 1;
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} else if (type == ID($neg)) {
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return 4;
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} else if (type == ID($demux)) {
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return 2;
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} else if (type == ID($fa)) {
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return 5;
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} else if (type.in(ID($add), ID($sub), ID($alu))) {
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// multi-bit adders
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return 8;
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} else if (type.in(ID($shl), ID($sshl))) {
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// left shift
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return 10;
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}
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return 0;
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}
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static unsigned int max_inp_coef(RTLIL::IdString type)
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{
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if (
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// binop reduce
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type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)) ||
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// others
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type.in(ID($logic_not), ID($pmux), ID($bmux))) {
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return 1;
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} else if (
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// equality
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type.in(ID($eq), ID($ne)) ||
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// logic
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type.in(ID($logic_and), ID($logic_or))) {
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return 2;
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} else if (type == ID($lcu)) {
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return 5;
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} else if (type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
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// comparison
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return 7;
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}
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return 0;
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}
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static unsigned int sum_coef(RTLIL::IdString type)
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{
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if (type.in(ID($shr), ID($sshr))) {
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// right shift
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return 4;
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} else if (type.in(ID($shift), ID($shiftx))) {
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// shift
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return 8;
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}
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return 0;
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}
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static unsigned int is_div_mod(RTLIL::IdString type)
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{
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return (type == ID($div) || type == ID($divfloor) || type == ID($mod) || type == ID($modfloor));
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}
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static bool is_free(RTLIL::IdString type)
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{
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return (
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// tags
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type.in(ID($overwrite_tag), ID($set_tag), ID($original_tag), ID($get_tag)) ||
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// formal
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type.in(ID($check), ID($equiv), ID($initstate), ID($assert), ID($assume), ID($live), ID($cover), ID($fair)) ||
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type.in(ID($allseq), ID($allconst), ID($anyseq), ID($anyconst), ID($anyinit)) ||
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// utilities
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type.in(ID($scopeinfo), ID($print)) ||
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// real but free
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type.in(ID($concat), ID($slice), ID($pos)) ||
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// specify
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type.in(ID($specrule), ID($specify2), ID($specify3)));
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}
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unsigned int max_inp_width(RTLIL::Cell *cell)
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{
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unsigned int max = 0;
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RTLIL::IdString input_width_params[] = {
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ID::WIDTH,
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ID::A_WIDTH,
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ID::B_WIDTH,
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ID::S_WIDTH,
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};
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if (cell->type == ID($bmux))
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return cell->getParam(ID::WIDTH).as_int() << cell->getParam(ID::S_WIDTH).as_int();
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for (RTLIL::IdString param : input_width_params)
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if (cell->hasParam(param))
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max = std::max(max, (unsigned int)cell->getParam(param).as_int());
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return max;
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}
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unsigned int port_width_sum(RTLIL::Cell *cell)
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{
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unsigned int sum = 0;
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RTLIL::IdString port_width_params[] = {
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ID::WIDTH, ID::A_WIDTH, ID::B_WIDTH, ID::S_WIDTH, ID::Y_WIDTH,
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};
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for (auto param : port_width_params)
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if (cell->hasParam(param))
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sum += cell->getParam(param).as_int();
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return sum;
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}
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unsigned int CellCosts::get(RTLIL::Cell *cell)
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{
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// simple 1-bit cells
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if (cmos_gate_cost().count(cell->type))
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return 1;
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if (design_ && design_->module(cell->type) && cell->parameters.empty()) {
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log_debug("%s is a module, recurse\n", cell->name.c_str());
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return get(design_->module(cell->type));
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} else if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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log_assert(cell->hasPort(ID::Q) && "Weird flip flop");
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log_debug("%s is ff\n", cell->name.c_str());
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return cell->getParam(ID::WIDTH).as_int();
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} else if (y_coef(cell->type)) {
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// linear with Y_WIDTH or WIDTH
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log_assert((cell->hasParam(ID::Y_WIDTH) || cell->hasParam(ID::WIDTH)) && "Unknown width");
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auto param = cell->hasParam(ID::Y_WIDTH) ? ID::Y_WIDTH : ID::WIDTH;
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int width = cell->getParam(param).as_int();
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if (cell->type == ID($demux))
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width <<= cell->getParam(ID::S_WIDTH).as_int();
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log_debug("%s Y*coef %d * %d\n", cell->name.c_str(), width, y_coef(cell->type));
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return width * y_coef(cell->type);
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} else if (sum_coef(cell->type)) {
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// linear with sum of port widths
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unsigned int sum = port_width_sum(cell);
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log_debug("%s sum*coef %d * %d\n", cell->name.c_str(), sum, sum_coef(cell->type));
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return sum * sum_coef(cell->type);
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} else if (max_inp_coef(cell->type)) {
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// linear with largest input width
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unsigned int max = max_inp_width(cell);
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log_debug("%s max*coef %d * %d\n", cell->name.c_str(), max, max_inp_coef(cell->type));
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return max * max_inp_coef(cell->type);
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} else if (is_div_mod(cell->type) || cell->type == ID($mul)) {
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// quadratic with sum of port widths
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unsigned int sum = port_width_sum(cell);
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unsigned int coef = cell->type == ID($mul) ? 3 : 5;
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log_debug("%s coef*(sum**2) %d * %d\n", cell->name.c_str(), coef, sum * sum);
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return coef * sum * sum;
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} else if (cell->type == ID($lut)) {
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int width = cell->getParam(ID::WIDTH).as_int();
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unsigned int cost = 1U << (unsigned int)width;
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log_debug("%s is 2**%d\n", cell->name.c_str(), width);
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return cost;
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} else if (cell->type == ID($sop)) {
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int width = cell->getParam(ID::WIDTH).as_int();
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int depth = cell->getParam(ID::DEPTH).as_int();
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log_debug("%s is (2*%d + 1)*%d\n", cell->name.c_str(), width, depth);
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return (2 * width + 1) * depth;
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} else if (is_free(cell->type)) {
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log_debug("%s is free\n", cell->name.c_str());
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return 0;
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}
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// TODO: $fsm $mem.* $macc
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// ignored: $pow
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log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
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return 1;
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}
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@ -26,7 +26,17 @@ YOSYS_NAMESPACE_BEGIN
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struct CellCosts
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{
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private:
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dict<RTLIL::IdString, int> mod_cost_cache_;
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Design *design_ = nullptr;
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public:
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CellCosts(RTLIL::Design *design) : design_(design) { }
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static const dict<RTLIL::IdString, int>& default_gate_cost() {
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// Default size heuristics for several common PDK standard cells
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// used by abc and stat
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static const dict<RTLIL::IdString, int> db = {
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{ ID($_BUF_), 1 },
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{ ID($_NOT_), 2 },
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@ -43,12 +53,14 @@ struct CellCosts
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{ ID($_AOI4_), 7 },
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{ ID($_OAI4_), 7 },
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{ ID($_MUX_), 4 },
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{ ID($_NMUX_), 4 }
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{ ID($_NMUX_), 4 },
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};
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return db;
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}
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static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
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// Estimated CMOS transistor counts for several common PDK standard cells
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// used by stat and optionally by abc
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static const dict<RTLIL::IdString, int> db = {
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{ ID($_BUF_), 1 },
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{ ID($_NOT_), 2 },
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@ -65,50 +77,21 @@ struct CellCosts
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{ ID($_AOI4_), 8 },
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{ ID($_OAI4_), 8 },
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{ ID($_MUX_), 12 },
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{ ID($_NMUX_), 10 }
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{ ID($_NMUX_), 10 },
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{ ID($_DFF_P_), 16 },
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{ ID($_DFF_N_), 16 },
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};
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return db;
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}
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dict<RTLIL::IdString, int> mod_cost_cache;
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const dict<RTLIL::IdString, int> *gate_cost = nullptr;
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Design *design = nullptr;
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int get(RTLIL::IdString type) const
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{
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if (gate_cost && gate_cost->count(type))
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return gate_cost->at(type);
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log_warning("Can't determine cost of %s cell.\n", log_id(type));
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return 1;
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}
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int get(RTLIL::Cell *cell)
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{
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if (gate_cost && gate_cost->count(cell->type))
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return gate_cost->at(cell->type);
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if (design && design->module(cell->type) && cell->parameters.empty())
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{
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RTLIL::Module *mod = design->module(cell->type);
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if (mod->attributes.count(ID(cost)))
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return mod->attributes.at(ID(cost)).as_int();
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if (mod_cost_cache.count(mod->name))
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return mod_cost_cache.at(mod->name);
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int module_cost = 1;
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for (auto c : mod->cells())
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module_cost += get(c);
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mod_cost_cache[mod->name] = module_cost;
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return module_cost;
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}
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log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
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return 1;
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}
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// Get the cell cost for a cell based on its parameters.
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// This cost is an *approximate* upper bound for the number of gates that
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// the cell will get mapped to with "opt -fast; techmap"
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// The intended usage is for flattening heuristics and similar situations
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unsigned int get(RTLIL::Cell *cell);
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// Sum up the cell costs of all cells in the module
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// and all its submodules recursively
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unsigned int get(RTLIL::Module *mod);
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};
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YOSYS_NAMESPACE_END
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