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Add more robsutness tests.
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17
tests/csa_tree/csa_tree_idempotent.ys
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17
tests/csa_tree/csa_tree_idempotent.ys
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# Running csa_tree twice, verify nothing changes on second run
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read_verilog add_chain_8.v
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hierarchy -auto-top
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proc; opt_clean
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csa_tree
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stat
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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csa_tree
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stat
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$sub
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44
tests/csa_tree/csa_tree_sub_double_neg.ys
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44
tests/csa_tree/csa_tree_sub_double_neg.ys
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# Test double negation
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read_verilog sub_double_neg.v
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hierarchy -auto-top
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proc; opt_clean
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csa_tree
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stat
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$sub
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design -reset
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# equiv_opt on narrow version
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read_verilog equiv_sub_double_neg.v
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hierarchy -top equiv_sub_double_neg
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proc; opt_clean
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equiv_opt csa_tree
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design -load postopt
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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# sat-prove on full width
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read_verilog sub_double_neg.v
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hierarchy -top sub_double_neg
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proc; opt_clean
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csa_tree
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opt_clean
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# 10 - (30 - 20) = 10 - 10 = 0
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sat -set a 30 -set b 20 -set c 10 -prove y 0
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# 100 - (50 - 25) = 100 - 25 = 75
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sat -set a 50 -set b 25 -set c 100 -prove y 75
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# 0 - (0 - 0) = 0
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sat -set a 0 -set b 0 -set c 0 -prove y 0
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# 1 - (255 - 1) = 1 - 254 = 3
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sat -set a 255 -set b 1 -set c 1 -prove y 3
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log "double negation: ok"
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7
tests/csa_tree/equiv_sub_double_neg.v
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7
tests/csa_tree/equiv_sub_double_neg.v
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module equiv_sub_double_neg(
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input [3:0] a, b, c,
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output [3:0] y
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);
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wire [3:0] ab = a - b;
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assign y = c - ab;
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endmodule
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7
tests/csa_tree/sub_double_neg.v
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7
tests/csa_tree/sub_double_neg.v
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module sub_double_neg(
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input [7:0] a, b, c,
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output [7:0] y
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);
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wire [7:0] ab = a - b;
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assign y = c - ab;
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endmodule
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