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Merge branch 'eddie/fix_retime' into xc7srl

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Eddie Hung 2019-04-05 16:30:17 -07:00
commit 4afcad70e2
2 changed files with 7 additions and 1 deletions
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2
passes/techmap/abc.cc
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@ -1728,7 +1728,7 @@ struct AbcPass : public Pass {
signal_init[initsig[i]] = State::S0; signal_init[initsig[i]] = State::S0;
break; break;
case State::S1: case State::S1:
signal_init[initsig[i]] = State::S0; signal_init[initsig[i]] = State::S1;
break; break;
default: default:
break; break;

6
tests/simple/retime.v Normal file
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@ -0,0 +1,6 @@
module retime_test(input clk, input [7:0] a, output z);
reg [7:0] ff = 8'hF5;
always @(posedge clk)
ff <= {ff[6:0], ^a};
assign z = ff[7];
endmodule