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coolrunner2: Initial mapping of DFFs

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All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N
(negative-edge triggered)
This commit is contained in:
Robert Ou 2017-06-25 20:16:43 -07:00
parent 1eb5dee799
commit 4af5baab21
4 changed files with 76 additions and 0 deletions
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1
techlibs/coolrunner2/Makefile.inc
View file

@ -3,3 +3,4 @@ OBJS += techlibs/coolrunner2/synth_coolrunner2.o
OBJS += techlibs/coolrunner2/coolrunner2_sop.o OBJS += techlibs/coolrunner2/coolrunner2_sop.o
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v)) $(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/cells_sim.v))
$(eval $(call add_share_file,share/coolrunner2,techlibs/coolrunner2/xc2_dff.lib))

40
techlibs/coolrunner2/cells_sim.v
View file

@ -54,3 +54,43 @@ module MACROCELL_XOR(IN_PTC, IN_ORTERM, OUT);
assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed; assign OUT = INVERT_OUT ? ~xor_intermed : xor_intermed;
assign xor_intermed = IN_ORTERM ^ IN_PTC; assign xor_intermed = IN_ORTERM ^ IN_PTC;
endmodule endmodule
module FDCP (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module FDCP_N (C, PRE, CLR, D, Q);
parameter INIT = 0;
input C, PRE, CLR, D;
output reg Q;
initial begin
Q <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else
Q <= D;
end
endmodule

4
techlibs/coolrunner2/synth_coolrunner2.cpp
View file

@ -145,6 +145,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
{ {
run("opt -fast -full"); run("opt -fast -full");
run("techmap"); run("techmap");
run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
} }
if (check_label("map_pla")) if (check_label("map_pla"))
@ -156,6 +157,9 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("map_cells")) if (check_label("map_cells"))
{ {
run("dfflibmap -liberty +/coolrunner2/xc2_dff.lib");
run("dffinit -ff FDCP Q INIT");
run("dffinit -ff FDCP_N Q INIT");
run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO"); run("iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO");
} }

31
techlibs/coolrunner2/xc2_dff.lib Normal file
View file

@ -0,0 +1,31 @@
library(xc2_dff) {
cell(FDCP) {
area: 1;
ff("IQ", "IQN") { clocked_on: C;
next_state: D;
clear: "CLR";
preset: "PRE"; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(CLR) { direction: input; }
pin(PRE) { direction: input; }
}
cell(FDCP_N) {
area: 1;
ff("IQ", "IQN") { clocked_on: "!C";
next_state: D;
clear: "CLR";
preset: "PRE"; }
pin(C) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
pin(CLR) { direction: input; }
pin(PRE) { direction: input; }
}
}