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Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor

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opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
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Eddie Hung 2020-04-01 14:17:01 -07:00 • committed by GitHub
commit 4ae7f3a8ed
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4 changed files with 92 additions and 10 deletions
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5
tests/arch/anlogic/fsm.ys
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@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT2
select -assert-count 5 t:AL_MAP_LUT5
select -assert-count 1 t:AL_MAP_LUT6
select -assert-count 6 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D

5
tests/arch/efinix/fsm.ys
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@ -10,7 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 6 t:EFX_FF
select -assert-count 15 t:EFX_LUT4
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 6 t:EFX_FF
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D

52
tests/opt/opt_expr_xor.ys Normal file
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@ -0,0 +1,52 @@
read_verilog <<EOT
module top(input a, output [3:0] y);
assign y[0] = a^1'b0;
assign y[1] = 1'b1^a;
assign y[2] = a~^1'b0;
assign y[3] = 1'b1^~a;
endmodule
EOT
design -save read
select -assert-count 2 t:$xor
select -assert-count 2 t:$xnor
equiv_opt opt_expr
design -load postopt
select -assert-none t:$xor
select -assert-none t:$xnor
select -assert-count 2 t:$not
design -load read
simplemap
equiv_opt opt_expr
design -load postopt
select -assert-none t:$_XOR_
select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
select -assert-count 3 t:$_NOT_
design -reset
read_verilog -icells <<EOT
module top(input a, output [1:0] y);
$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0]));
$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
endmodule
EOT
select -assert-count 2 t:$_XNOR_
equiv_opt opt_expr
design -load postopt
select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
select -assert-count 1 t:$_NOT_
design -reset
read_verilog <<EOT
module top(input a, output [1:0] w, x, y, z);
assign w = a^1'b0;
assign x = a^1'b1;
assign y = a~^1'b0;
assign z = a~^1'b1;
endmodule
EOT
equiv_opt opt_expr