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Bugfixes in writing of memories as Verilog

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This commit is contained in:
Clifford Wolf 2015-09-25 13:49:26 +02:00
parent b2544cfcf7
commit 4ac202e2a5
1 changed files with 8 additions and 7 deletions
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15
backends/verilog/verilog_backend.cc
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@ -165,12 +165,13 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
log_assert(i < (int)data.bits.size()); log_assert(i < (int)data.bits.size());
if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1) if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
goto dump_bits; goto dump_bits;
if (data.bits[i] == RTLIL::S1 && (i - offset) == 31)
goto dump_bits;
if (data.bits[i] == RTLIL::S1) if (data.bits[i] == RTLIL::S1)
val |= 1 << (i - offset); val |= 1 << (i - offset);
} }
f << stringf("32'%sd %d", set_signed ? "s" : "", val); if (set_signed && val < 0)
f << stringf("-32'sd %u", -val);
else
f << stringf("32'%sd %u", set_signed ? "s" : "", val);
} else { } else {
dump_bits: dump_bits:
f << stringf("%d'%sb", width, set_signed ? "s" : ""); f << stringf("%d'%sb", width, set_signed ? "s" : "");
@ -805,15 +806,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// initial begin // initial begin
// memid[0] <= ... // memid[0] <= ...
// end // end
int mem_val;
f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size-1, 0); f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size-1, 0);
if (use_init) if (use_init)
{ {
f << stringf("%s" "initial begin\n", indent.c_str()); f << stringf("%s" "initial begin\n", indent.c_str());
for (int i=0; i<size; i++) for (int i=0; i<size; i++)
{ {
mem_val = cell->parameters["\\INIT"].extract(i*width, width).as_int(); f << stringf("%s" " %s[%d] <= ", indent.c_str(), mem_id.c_str(), i);
f << stringf("%s" " %s[%d] <= %d'd%d;\n", indent.c_str(), mem_id.c_str(), i, width, mem_val); dump_const(f, cell->parameters["\\INIT"].extract(i*width, width));
f << stringf(";\n");
} }
f << stringf("%s" "end\n", indent.c_str()); f << stringf("%s" "end\n", indent.c_str());
} }
@ -884,7 +885,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
std::ostringstream os; std::ostringstream os;
dump_sigspec(os, sig_rd_data); dump_sigspec(os, sig_rd_data);
std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str()); std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str());
clk_to_lof_body[clk_domain_str].push_back(line); clk_to_lof_body[""].push_back(line);
} }
} else { } else {
// for non-clocked read-ports make something like: // for non-clocked read-ports make something like: