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cutpoint: Track wire drivers

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Necessary to avoid multiple drivers being inserted when a blackbox has inout ports (like when importing an unknown module with `verific`).
If any bits of an inout port have a known driver, treat the port as an input.
If there are no bits with a known driver, treat the port as an output, and mark each bit as having a driver.
This commit is contained in:
Krystine Sherwin 2025-08-06 18:11:05 +12:00
parent 1bf9530fcc
commit 4ac100fe13
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1 changed files with 32 additions and 2 deletions
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34
passes/sat/cutpoint.cc
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@ -109,13 +109,43 @@ struct CutpointPass : public Pass {
SigMap sigmap(module); SigMap sigmap(module);
pool<SigBit> cutpoint_bits; pool<SigBit> cutpoint_bits;
pool<SigBit> wire_drivers;
for (auto cell : module->cells())
for (auto &conn : cell->connections())
if (cell->output(conn.first) && !cell->input(conn.first))
for (auto bit : sigmap(conn.second))
if (bit.wire)
wire_drivers.insert(bit);
for (auto wire : module->wires())
if (wire->port_input)
for (auto bit : sigmap(wire))
wire_drivers.insert(bit);
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
if (cell->type == ID($anyseq)) if (cell->type == ID($anyseq))
continue; continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell)); log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
if (cell->output(conn.first)) if (cell->output(conn.first)) {
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second))); bool do_cut = true;
if (cell->input(conn.first))
for (auto bit : sigmap(conn.second))
if (wire_drivers.count(bit)) {
log_debug(" Treating inout port '%s' as input.\n", id2cstr(conn.first));
do_cut = false;
break;
}
if (do_cut) {
module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
if (cell->input(conn.first)) {
log_debug(" Treating inout port '%s' as output.\n", id2cstr(conn.first));
for (auto bit : sigmap(conn.second))
wire_drivers.insert(bit);
}
}
}
} }
RTLIL::Cell *scopeinfo = nullptr; RTLIL::Cell *scopeinfo = nullptr;