mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-27 14:37:55 +00:00
start adding wfg model
This commit is contained in:
parent
41a86fdb2c
commit
4aaab8f395
2 changed files with 49 additions and 23 deletions
|
@ -539,27 +539,6 @@ module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3,
|
|||
parameter use_pll = 1'b1;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module NX_WFG_U(R, SI, ZI, SO, ZO);
|
||||
input R;
|
||||
input SI;
|
||||
output SO;
|
||||
input ZI;
|
||||
output ZO;
|
||||
parameter delay = 0;
|
||||
parameter delay_on = 1'b0;
|
||||
parameter div_phase = 1'b0;
|
||||
parameter div_ratio = 0;
|
||||
parameter location = "";
|
||||
parameter mode = 0;
|
||||
parameter pattern = 16'b0000000000000000;
|
||||
parameter pattern_end = 0;
|
||||
parameter reset_on_cal_lock_n = 1'b0;
|
||||
parameter reset_on_pll_lock_n = 1'b0;
|
||||
parameter reset_on_pll_locka_n = 1'b0;
|
||||
parameter wfg_edge = 1'b0;
|
||||
endmodule
|
||||
|
||||
(* blackbox *)
|
||||
module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
|
||||
, AO, BO, AI, DI, DO);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue