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Change how to specify flops to ABC again
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3 changed files with 63 additions and 33 deletions
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@ -86,23 +86,35 @@ module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q);
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// assign Q = S ? B : A;
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endmodule
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(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
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module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
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(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
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module \$__ABC_FDRE ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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(* abc_flop_clk_inv *) parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
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endmodule
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(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
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module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
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(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1" *)
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module \$__ABC_FDRE_1 ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
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endmodule
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(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
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module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
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(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE" *)
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module \$__ABC_FDCE ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input CLR, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -110,14 +122,22 @@ module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
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assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
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module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
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(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1" *)
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module \$__ABC_FDCE_1 ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input CLR, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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assign Q = (CE && !CLR) ? D : \$pastQ ;
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endmodule
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(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
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module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
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(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE" *)
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module \$__ABC_FDPE ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input PRE, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -125,8 +145,12 @@ module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
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assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
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module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
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(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1" *)
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module \$__ABC_FDPE_1 ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input PRE, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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assign Q = (CE && !PRE) ? D : \$pastQ ;
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endmodule
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