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Change how to specify flops to ABC again

This commit is contained in:
Eddie Hung 2019-07-10 17:54:56 -07:00
parent a092c48f03
commit 4a995c5d80
3 changed files with 63 additions and 33 deletions

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@ -86,23 +86,35 @@ module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q);
// assign Q = S ? B : A;
endmodule
(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *)
module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
module \$__ABC_FDRE ((* abc_flop_q *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
(* abc_flop_clk_inv *) parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
endmodule
(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDRE_1 (output Q, input C, CE, D, R, \$pastQ );
(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1" *)
module \$__ABC_FDRE_1 ((* abc_flop_q *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input R, \$pastQ );
parameter [0:0] INIT = 1'b0;
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
endmodule
(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE,D,Q,\\$pastQ" *)
module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE" *)
module \$__ABC_FDCE ((* abc_flop_q *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -110,14 +122,22 @@ module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1" *)
module \$__ABC_FDCE_1 ((* abc_flop_q *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input CLR, \$pastQ );
parameter [0:0] INIT = 1'b0;
assign Q = (CE && !CLR) ? D : \$pastQ ;
endmodule
(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE" *)
module \$__ABC_FDPE ((* abc_flop_q *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
@ -125,8 +145,12 @@ module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule
(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1" *)
module \$__ABC_FDPE_1 ((* abc_flop_q *) output Q,
(* abc_flop_clk *) input C,
(* abc_flop_en *) input CE,
(* abc_flop_d *) input D,
input PRE, \$pastQ );
parameter [0:0] INIT = 1'b0;
assign Q = (CE && !PRE) ? D : \$pastQ ;
endmodule