3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-02 08:10:46 +00:00

proc_clean: fix order of switch insertion.

Fixes #1268.
This commit is contained in:
whitequark 2019-08-19 16:44:23 +00:00
parent 4adcbecec5
commit 4a942ba7b9
6 changed files with 37 additions and 2 deletions

5
tests/proc/bug_1268.ys Normal file
View file

@ -0,0 +1,5 @@
read_verilog bug_1268.v
proc
equiv_make gold gate equiv
equiv_induct
equiv_status -assert