From 4a7878b17fdddc686ccc29033385d02262e8f056 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 14 May 2026 15:58:58 +0200 Subject: [PATCH] Fixing couple more conversion errors --- frontends/ast/ast.cc | 2 +- passes/cmds/design.cc | 4 ++-- passes/cmds/rename.cc | 8 ++++---- passes/techmap/techmap.cc | 2 +- techlibs/quicklogic/ql_dsp_macc.cc | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 256321252..f5a601c3a 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1584,7 +1584,7 @@ bool AstModule::reprocess_if_necessary(RTLIL::Design *design) continue; if (design->module(modname) || design->module("$abstract" + modname)) { log("Reprocessing module %s because instantiated module %s has become available.\n", - name.unescape(), modname); + name.unescape(), RTLIL::unescape_id(modname)); loadconfig(); process_and_replace_module(design, this, ast.get(), NULL); return true; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 68b778790..cfd5d8af8 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -266,7 +266,7 @@ struct DesignPass : public Pass { for (auto mod : copy_src_modules) { - log("Importing %s as %s.\n", mod, prefix); + log("Importing %s as %s.\n", mod, RTLIL::unescape_id(prefix)); RTLIL::Module *t = mod->clone(); t->name = prefix; @@ -295,7 +295,7 @@ struct DesignPass : public Pass { { std::string trg_name = prefix + "." + (cell->type.c_str() + (*cell->type.c_str() == '\\')); - log("Importing %s as %s.\n", fmod, trg_name); + log("Importing %s as %s.\n", fmod, RTLIL::unescape_id(trg_name)); if (copy_to_design->module(trg_name) != nullptr) copy_to_design->remove(copy_to_design->module(trg_name)); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 15b6bf539..2f70126dd 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -31,13 +31,13 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: to_name = RTLIL::escape_id(to_name); if (module->count_id(to_name)) - log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name, module->name); + log_cmd_error("There is already an object `%s' in module `%s'.\n", RTLIL::unescape_id(to_name), module->name); RTLIL::Wire *wire_to_rename = module->wire(from_name); RTLIL::Cell *cell_to_rename = module->cell(from_name); if (wire_to_rename != nullptr) { - log("Renaming wire %s to %s in module %s.\n", wire_to_rename, to_name, module); + log("Renaming wire %s to %s in module %s.\n", wire_to_rename, RTLIL::unescape_id(to_name), module); module->rename(wire_to_rename, to_name); if (wire_to_rename->port_id || flag_output) { if (flag_output) @@ -50,12 +50,12 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: if (cell_to_rename != nullptr) { if (flag_output) log_cmd_error("Called with -output but the specified object is a cell.\n"); - log("Renaming cell %s to %s in module %s.\n", cell_to_rename, to_name, module); + log("Renaming cell %s to %s in module %s.\n", cell_to_rename, RTLIL::unescape_id(to_name), module); module->rename(cell_to_rename, to_name); return; } - log_cmd_error("Object `%s' not found!\n", from_name); + log_cmd_error("Object `%s' not found!\n", RTLIL::unescape_id(from_name)); } static std::string derive_name_from_src(const std::string &src, int counter) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 5827feb92..e975d2fd2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1265,7 +1265,7 @@ struct TechmapPass : public Pass { i.second.sort(RTLIL::sort_by_id_str()); std::string maps = ""; for (auto &map : i.second) - maps += stringf(" %s", map); + maps += stringf(" %s", map.unescape()); log_debug(" %s:%s\n", i.first.unescape(), maps); } log_debug("\n"); diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index febfaddf1..083dc3ff1 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -73,7 +73,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) } type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports"); - log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, type); + log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, type.unescape()); for (auto cell : {st.mul, st.add, st.mux, st.ff}) if (cell)