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This commit is contained in:
Eddie Hung 2019-05-28 08:44:59 -07:00
parent 89bd6b8504
commit 4a76b425cc
1 changed files with 1 additions and 1 deletions
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passes/techmap/abc9.cc
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@ -567,7 +567,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// Attempt another wideports_split here because there // Attempt another wideports_split here because there
// exists the possibility that different bits of a port // exists the possibility that different bits of a port
// could be an input and output, therefore parse_xiager() // could be an input and output, therefore parse_xaiger()
// could not combine it into a wideport // could not combine it into a wideport
auto r = wideports_split(w->name.str()); auto r = wideports_split(w->name.str());
wire = module->wire(r.first); wire = module->wire(r.first);