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Fixup parameters

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This commit is contained in:
Akash Levy 2025-11-06 07:50:59 -08:00
parent 266854aa64
commit 4a69969df4
1 changed files with 3 additions and 0 deletions
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3
passes/techmap/abc.cc
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@ -1492,6 +1492,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
cell->fixup_parameters();
design->select(module, cell);
continue;
}
@ -1513,6 +1514,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
cell->fixup_parameters();
design->select(module, cell);
continue;
}
@ -1530,6 +1532,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
cell->setPort(name, module->wire(remapped_name));
}
cell->fixup_parameters();
design->select(module, cell);
continue;
}