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ecp5: Cells and mappings fixes

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-13 16:14:08 +02:00
parent b0fea67cc6
commit 4a60bc83ab
2 changed files with 5 additions and 5 deletions
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4
techlibs/ecp5/cells_sim.v
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@ -103,7 +103,7 @@ module TRELLIS_DPR16X4 (
integer i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] <= INITVAL[4*i :+ 4];
mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
end
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
@ -197,7 +197,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
initial Q = srval;