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Refactor demo_reduce into test_pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-08-16 11:47:51 +02:00
parent 016036f247
commit 4a57b7e1ab
4 changed files with 83 additions and 14 deletions

View file

@ -1,3 +1,3 @@
/demo_reduce_pm.h /test_pmgen_pm.h
/ice40_dsp_pm.h /ice40_dsp_pm.h
/peepopt_pm.h /peepopt_pm.h

View file

@ -9,9 +9,9 @@ $(eval $(call add_extra_objs,passes/pmgen/ice40_dsp_pm.h))
# -------------------------------------- # --------------------------------------
OBJS += passes/pmgen/demo_reduce.o OBJS += passes/pmgen/test_pmgen.o
passes/pmgen/demo_reduce.o: passes/pmgen/demo_reduce_pm.h passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h
$(eval $(call add_extra_objs,passes/pmgen/demo_reduce_pm.h)) $(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
# -------------------------------------- # --------------------------------------

View file

@ -23,9 +23,9 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
#include "passes/pmgen/demo_reduce_pm.h" #include "passes/pmgen/test_pmgen_pm.h"
void create_reduce(demo_reduce_pm &pm) void reduce_chain(test_pmgen_pm &pm)
{ {
auto &st = pm.st_reduce; auto &st = pm.st_reduce;
auto &ud = pm.ud_reduce; auto &ud = pm.ud_reduce;
@ -65,23 +65,58 @@ void create_reduce(demo_reduce_pm &pm)
log(" -> %s (%s)\n", log_id(c), log_id(c->type)); log(" -> %s (%s)\n", log_id(c), log_id(c->type));
} }
struct DemoReducePass : public Pass { void reduce_tree(test_pmgen_pm &pm)
DemoReducePass() : Pass("demo_reduce", "map chains of AND/OR/XOR") { } {
auto &st = pm.st_reduce;
auto &ud = pm.ud_reduce;
if (ud.longest_chain.empty())
return;
SigSpec A = ud.leaves;
SigSpec Y = st.first->getPort(ID(Y));
pm.autoremove(st.first);
log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type),
GetSize(A), log_signal(Y), log_id(st.first));
Cell *c;
if (st.first->type == ID($_AND_))
c = pm.module->addReduceAnd(NEW_ID, A, Y);
else if (st.first->type == ID($_OR_))
c = pm.module->addReduceOr(NEW_ID, A, Y);
else if (st.first->type == ID($_XOR_))
c = pm.module->addReduceXor(NEW_ID, A, Y);
else
log_abort();
log(" -> %s (%s)\n", log_id(c), log_id(c->type));
}
struct TestPmgenPass : public Pass {
TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { }
void help() YS_OVERRIDE void help() YS_OVERRIDE
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" demo_reduce [options] [selection]\n"); log(" test_pmgen -reduce_chain [options] [selection]\n");
log("\n"); log("\n");
log("Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to $reduce_*.\n"); log("Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to $reduce_*.\n");
log("\n"); log("\n");
log("\n");
log(" test_pmgen -reduce_tree [options] [selection]\n");
log("\n");
log("Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
void execute_reduce_chain(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header(design, "Executing DEMO_REDUCE pass.\n"); log_header(design, "Executing TEST_PMGEN pass (-reduce_chain).\n");
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 2; argidx < args.size(); argidx++)
{ {
// if (args[argidx] == "-singleton") { // if (args[argidx] == "-singleton") {
// singleton_mode = true; // singleton_mode = true;
@ -92,8 +127,39 @@ struct DemoReducePass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
demo_reduce_pm(module, module->selected_cells()).run_reduce(create_reduce); test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_chain);
} }
} DemoReducePass;
void execute_reduce_tree(std::vector<std::string> args, RTLIL::Design *design)
{
log_header(design, "Executing TEST_PMGEN pass (-reduce_tree).\n");
size_t argidx;
for (argidx = 2; argidx < args.size(); argidx++)
{
// if (args[argidx] == "-singleton") {
// singleton_mode = true;
// continue;
// }
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree);
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
if (GetSize(args) > 1)
{
if (args[1] == "-reduce_chain")
return execute_reduce_chain(args, design);
if (args[1] == "-reduce_tree")
return execute_reduce_tree(args, design);
}
log_cmd_error("Missing or unsupported mode parameter.\n");
}
} TestPmgenPass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END

View file

@ -3,6 +3,7 @@ pattern reduce
state <IdString> portname state <IdString> portname
udata <vector<pair<Cell*, IdString>>> chain longest_chain udata <vector<pair<Cell*, IdString>>> chain longest_chain
udata <pool<Cell*>> non_first_cells udata <pool<Cell*>> non_first_cells
udata <SigSpec> leaves
code code
non_first_cells.clear(); non_first_cells.clear();
@ -15,6 +16,7 @@ match first
endmatch endmatch
code code
leaves = SigSpec();
longest_chain.clear(); longest_chain.clear();
chain.push_back(make_pair(first, \A)); chain.push_back(make_pair(first, \A));
subpattern(tail); subpattern(tail);
@ -73,6 +75,7 @@ code
} else { } else {
if (GetSize(chain) > GetSize(longest_chain)) if (GetSize(chain) > GetSize(longest_chain))
longest_chain = chain; longest_chain = chain;
leaves.append(port(chain.back().first, chain.back().second));
} }
finally finally
if (next) if (next)