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Various improvements in support for generate statements

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This commit is contained in:
Clifford Wolf 2013-12-04 21:06:54 +01:00
parent f4b46ed31e
commit 4a4a3fc337
7 changed files with 161 additions and 7 deletions
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1
frontends/ast/genrtlil.cc
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@ -812,6 +812,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENFOR:
case AST_GENBLOCK:
case AST_GENIF:
case AST_GENCASE:
break;
// remember the parameter, needed for example in techmap