Merge from upstream

tests/various/bug3515.v

@@ -0,0 +1,26 @@
+// Triple AND GATE
+module mod_74x08_3 (
+    input A_1,
+    input B_1,
+    input A_2,
+    input B_2,
+    input A_3,
+    input B_3,
+    output Y_1,
+    output Y_2,
+    output Y_3);
+
+assign Y_1 = A_1 & B_1;
+assign Y_2 = A_2 & B_2;
+assign Y_3 = A_3 & B_3;
+
+endmodule
+
+// OR GATE
+module mod_74x32_1 (
+    input A_1,
+    input B_1,
+    output Y_1);
+
+assign Y_1 = A_1 | B_1;
+endmodule

tests/various/bug3515.ys

@@ -0,0 +1,31 @@
+# base case is able to map
+read_verilog << EOF
+module and_x3 (
+    input a, b, c, d,
+    output reg y
+);
+
+assign y = (a&b)&(c&d);
+endmodule
+EOF
+hierarchy -top and_x3
+opt
+extract -map ./bug3515.v
+select -assert-count 1 t:mod_74x08_3
+
+# more needles than haystacks; not able to map
+design -reset
+read_verilog << EOF
+module mod_and_or (
+    input a, b, c, d,
+    output reg y
+);
+
+assign y = (a&b)|(c&d);
+endmodule
+EOF
+hierarchy -top mod_and_or
+opt
+extract -map ./bug3515.v
+select -assert-count 2 t:$and
+