diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 3d451117c..13f6acec4 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -421,6 +421,13 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 	}
 }
 
+void dump_parameter(std::ostream &f, std::string indent, RTLIL::IdString id_string, RTLIL::Const parameter)
+{
+	f << stringf("%sparameter %s = ", indent.c_str(), id(id_string).c_str());
+	dump_const(f, parameter);
+	f << ";\n";
+}
+
 void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 {
 	dump_attributes(f, indent, wire->attributes, "\n", /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name));
@@ -2438,6 +2445,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		f << indent + "  " << "reg " << id(initial_id) << " = 0;\n";
 	}
 
+	for (auto p : module->parameter_default_values)
+		dump_parameter(f, indent + "  ", p.first, p.second);
+
 	// first dump input / output according to their order in module->ports
 	for (auto port : module->ports)
 		dump_wire(f, indent + "  ", module->wire(port));
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc
index 743ac5d9e..803931f32 100644
--- a/frontends/json/jsonparse.cc
+++ b/frontends/json/jsonparse.cc
@@ -302,6 +302,9 @@ void json_import(Design *design, string &modname, JsonNode *node)
 	if (node->data_dict.count("attributes"))
 		json_parse_attr_param(module->attributes, node->data_dict.at("attributes"));
 
+	if (node->data_dict.count("parameter_default_values"))
+		json_parse_attr_param(module->parameter_default_values, node->data_dict.at("parameter_default_values"));
+
 	dict<int, SigBit> signal_bits;
 
 	if (node->data_dict.count("ports"))
diff --git a/tests/various/json_param_defaults.v b/tests/various/json_param_defaults.v
new file mode 100644
index 000000000..7d3b94a68
--- /dev/null
+++ b/tests/various/json_param_defaults.v
@@ -0,0 +1,10 @@
+module json_param_defaults #(
+	parameter WIDTH = 8,
+	parameter SIGNED = 1
+) (
+	input  [WIDTH-1:0] a,
+	output [WIDTH-1:0] y
+);
+	wire [WIDTH-1:0] y_int = a << SIGNED;
+	assign y = y_int;
+endmodule
diff --git a/tests/various/json_param_defaults.ys b/tests/various/json_param_defaults.ys
new file mode 100644
index 000000000..2624ab884
--- /dev/null
+++ b/tests/various/json_param_defaults.ys
@@ -0,0 +1,8 @@
+! mkdir -p temp
+read_verilog -sv json_param_defaults.v
+write_json temp/json_param_defaults.json
+design -reset
+read_json temp/json_param_defaults.json
+write_verilog -noattr temp/json_param_defaults.v
+! grep -qF "parameter WIDTH = 32'd8" temp/json_param_defaults.v
+! grep -qF "parameter SIGNED = 32'd1" temp/json_param_defaults.v