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Support SystemVerilog `` extension for macros

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This commit is contained in:
Jim Paris 2018-05-17 00:09:56 -04:00
parent 872d8d49e9
commit 4a229e5b95
1 changed files with 5 additions and 1 deletions
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6
frontends/verilog/preproc.cc
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@ -183,8 +183,9 @@ static std::string next_token(bool pass_newline = false)
const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789"; const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789";
if (ch == '`' || strchr(ok, ch) != NULL) if (ch == '`' || strchr(ok, ch) != NULL)
{ {
char first = ch;
ch = next_char(); ch = next_char();
if (ch == '"') { if (first == '`' && (ch == '"' || ch == '`')) {
token += ch; token += ch;
} else do { } else do {
if (strchr(ok, ch) == NULL) { if (strchr(ok, ch) == NULL) {
@ -265,6 +266,9 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
} }
insert_input(defines_map[name]); insert_input(defines_map[name]);
return true; return true;
} else if (tok == "``") {
// Swallow `` in macro expansion
return true;
} else return false; } else return false;
} }