mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 00:26:40 +00:00
Code Activity

remove not needed code

Browse source
This commit is contained in:
Alain Dargelas 2025-01-31 16:26:17 -08:00
parent 9a11df11ae
commit 4a1af2f780
1 changed files with 0 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/annotate_cell_fanout.cc
View file

@ -9,10 +9,6 @@ PRIVATE_NAMESPACE_BEGIN
void sigCellDrivers(RTLIL::Design *design, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout,
dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin)
{
if (!design->top_module())
return;
if (design->top_module()->cells().size() == 0)
return;
for (auto module : design->selected_modules()) {
SigMap sigmap(module);
for (auto cell : module->selected_cells()) {