From 4a10e78777a65c3fc18ffcba6e01bf5a62df81c0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Fri, 23 Feb 2024 10:44:41 +0100
Subject: [PATCH] celledges: Emit empty edges for write/init ports

---
 kernel/celledges.cc | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 598d7d806..48475cfdd 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -341,6 +341,18 @@ void memrd_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 			db->add_edge(cell, ID::ADDR, j, ID::DATA, k, -1);
 }
 
+void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	if (cell->type == ID($mem_v2))
+		packed_mem_op(db, cell);
+	else if (cell->type.in(ID($memrd), ID($memrd_v2)))
+		memrd_op(db, cell);
+	else if (cell->type.in(ID($memwr), ID($memwr_v2), ID($meminit)))
+		return; /* no edges here */
+	else
+		log_abort();
+}
+
 PRIVATE_NAMESPACE_END
 
 bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
@@ -395,13 +407,8 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 		return true;
 	}
 
-	if (cell->type == ID($mem_v2)) {
-		packed_mem_op(this, cell);
-		return true;
-	}
-
-	if (cell->type.in(ID($memrd), ID($memrd_v2))) {
-		memrd_op(this, cell);
+	if (cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2), ID($meminit))) {
+		mem_op(this, cell);
 		return true;
 	}