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https://github.com/YosysHQ/yosys
synced 2025-04-13 04:28:18 +00:00
xprop: Improve signal splitting code
Avoid splitting output ports twice when combining -split-outputs with -split-public and clean up the corresponding code.
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parent
6a6e1d8424
commit
4a0ed35aab
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@ -967,7 +967,7 @@ struct XpropWorker
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if (!options.split_inputs && !options.split_outputs)
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if (!options.split_inputs && !options.split_outputs)
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return;
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return;
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vector<IdString> new_ports;
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int port_id = 1;
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for (auto port : module->ports) {
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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auto wire = module->wire(port);
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@ -983,16 +983,21 @@ struct XpropWorker
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wire_d->port_input = wire->port_input;
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wire_d->port_input = wire->port_input;
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wire_d->port_output = wire->port_output;
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wire_d->port_output = wire->port_output;
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wire_d->port_id = GetSize(new_ports) + 1;
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wire_d->port_id = port_id++;
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wire_x->port_input = wire->port_input;
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wire_x->port_input = wire->port_input;
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wire_x->port_output = wire->port_output;
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wire_x->port_output = wire->port_output;
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wire_x->port_id = GetSize(new_ports) + 2;
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wire_x->port_id = port_id++;
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if (wire->port_output) {
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if (wire->port_output) {
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auto enc = encoded(wire);
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auto enc = encoded(wire);
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module->connect(wire_d, enc.is_1);
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module->connect(wire_d, enc.is_1);
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module->connect(wire_x, enc.is_x);
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module->connect(wire_x, enc.is_x);
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if (options.split_public) {
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// Need to hide the original wire so split_public doesn't try to split it again
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module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
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}
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} else {
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} else {
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auto enc = encoded(wire, true);
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auto enc = encoded(wire, true);
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@ -1004,18 +1009,12 @@ struct XpropWorker
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wire->port_input = wire->port_output = false;
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wire->port_input = wire->port_output = false;
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wire->port_id = 0;
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wire->port_id = 0;
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new_ports.push_back(port_d);
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new_ports.push_back(port_x);
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continue;
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continue;
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}
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}
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}
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}
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wire->port_id = GetSize(new_ports) + 1;
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wire->port_id = port_id++;
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new_ports.push_back(port);
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}
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}
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module->ports = new_ports;
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module->fixup_ports();
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module->fixup_ports();
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}
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}
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@ -1037,10 +1036,7 @@ struct XpropWorker
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module->connect(wire_d, enc.is_1);
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module->connect(wire_d, enc.is_1);
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module->connect(wire_x, enc.is_x);
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module->connect(wire_x, enc.is_x);
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module->wires_.erase(wire->name);
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module->rename(wire, NEW_ID_SUFFIX(wire->name.c_str()));
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wire->attributes.erase(ID::fsm_encoding);
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wire->name = NEW_ID_SUFFIX(wire->name.c_str());
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module->wires_[wire->name] = wire;
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}
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}
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}
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}
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