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Various small improvements to synth_xilinx

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This commit is contained in:
Clifford Wolf 2015-01-06 14:37:50 +01:00
parent 081e1a49f8
commit 4a0b3a5423
2 changed files with 8 additions and 10 deletions
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4
passes/techmap/iopadmap.cc
View file

@ -62,8 +62,8 @@ struct IopadmapPass : public Pass {
log("\n"); log("\n");
log(" -bits\n"); log(" -bits\n");
log(" create individual bit-wide buffers even for ports that\n"); log(" create individual bit-wide buffers even for ports that\n");
log(" are wider. (the default behavio is to create word-wide\n"); log(" are wider. (the default behavior is to create word-wide\n");
log(" buffers use -widthparam to set the word size on the cell.)\n"); log(" buffers using -widthparam to set the word size on the cell.)\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)

14
techlibs/xilinx/synth_xilinx.cc
View file

@ -74,8 +74,7 @@ struct SynthXilinxPass : public Pass {
log(" techmap -map +/xilinx/brams.v\n"); log(" techmap -map +/xilinx/brams.v\n");
log("\n"); log("\n");
log(" fine:\n"); log(" fine:\n");
log(" techmap\n"); log(" synth -run fine\n");
log(" opt -fast -full\n");
log("\n"); log("\n");
log(" map_luts:\n"); log(" map_luts:\n");
log(" abc -lut 6\n"); log(" abc -lut 6\n");
@ -91,11 +90,11 @@ struct SynthXilinxPass : public Pass {
log("\n"); log("\n");
log(" clkbuf:\n"); log(" clkbuf:\n");
log(" select -set xilinx_clocks <top>/t:FDRE %%x:+FDRE[C] <top>/t:FDRE %%d\n"); log(" select -set xilinx_clocks <top>/t:FDRE %%x:+FDRE[C] <top>/t:FDRE %%d\n");
log(" iopadmap -inpad BUFGP O:I @xilinx_clocks\n"); log(" iopadmap -bits -inpad BUFGP O:I @xilinx_clocks\n");
log("\n"); log("\n");
log(" iobuf:\n"); log(" iobuf:\n");
log(" select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %%x:+BUFGP[I] %%d\n"); log(" select -set xilinx_nonclocks <top>/w:* <top>/t:BUFGP %%x:+BUFGP[I] %%d\n");
log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n"); log(" iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n");
log("\n"); log("\n");
log(" edif:\n"); log(" edif:\n");
log(" write_edif synth.edif\n"); log(" write_edif synth.edif\n");
@ -171,8 +170,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "fine")) if (check_label(active, run_from, run_to, "fine"))
{ {
Pass::call(design, "techmap"); Pass::call(design, "synth -run fine");
Pass::call(design, "opt -fast -full");
} }
if (check_label(active, run_from, run_to, "map_luts")) if (check_label(active, run_from, run_to, "map_luts"))
@ -196,13 +194,13 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "clkbuf")) if (check_label(active, run_from, run_to, "clkbuf"))
{ {
Pass::call(design, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module.c_str(), top_module.c_str())); Pass::call(design, stringf("select -set xilinx_clocks %s/t:FDRE %%x:+FDRE[C] %s/t:FDRE %%d", top_module.c_str(), top_module.c_str()));
Pass::call(design, "iopadmap -inpad BUFGP O:I @xilinx_clocks"); Pass::call(design, "iopadmap -bits -inpad BUFGP O:I @xilinx_clocks");
} }
if (check_label(active, run_from, run_to, "iobuf")) if (check_label(active, run_from, run_to, "iobuf"))
{ {
Pass::call(design, stringf("select -set xilinx_nonclocks %s/w:* %s/t:BUFGP %%x:+BUFGP[I] %%d", top_module.c_str(), top_module.c_str())); Pass::call(design, stringf("select -set xilinx_nonclocks %s/w:* %s/t:BUFGP %%x:+BUFGP[I] %%d", top_module.c_str(), top_module.c_str()));
Pass::call(design, "iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks"); Pass::call(design, "iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks");
} }
if (check_label(active, run_from, run_to, "edif")) if (check_label(active, run_from, run_to, "edif"))