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read_rtlil: warn on assigns after switches in case rules

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This commit is contained in:
George Rennie 2024-11-21 20:51:05 +01:00
parent 4b3c03dabc
commit 4a057b3c44
3 changed files with 16 additions and 0 deletions
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10
frontends/rtlil/rtlil_parser.y
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@ -344,6 +344,16 @@ assign_stmt:
TOK_ASSIGN sigspec sigspec EOL {
if (attrbuf.size() != 0)
rtlil_frontend_yyerror("dangling attribute");
// See https://github.com/YosysHQ/yosys/pull/4765 for discussion on this
// warning
if (!switch_stack.back()->empty()) {
rtlil_frontend_yywarning(
"case rule assign statements after switch statements may cause unexpected behaviour. "
"The assign statement is reordered to come before all switch statements."
);
}
case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
delete $2;
delete $3;