mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Using new obj iterator API in a few places

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 10:41:42 +02:00
parent 675cb93da9
commit 49f72421d5
10 changed files with 85 additions and 87 deletions
Download patch file Download diff file Expand all files Collapse all files

26
passes/memory/memory_dff.cc
View file

@ -38,10 +38,8 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
if (bit.wire == NULL) if (bit.wire == NULL)
continue; continue;
for (auto &cell_it : module->cells_) for (auto cell : module->cells())
{ {
RTLIL::Cell *cell = cell_it.second;
if (cell->type != "$dff") if (cell->type != "$dff")
continue; continue;
@ -120,15 +118,13 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
for (auto &cell_it : module->cells_) { for (auto cell : module->cells())
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$dff") { if (cell->type == "$dff") {
RTLIL::SigSpec new_q = cell->get("\\Q"); RTLIL::SigSpec new_q = cell->get("\\Q");
new_q.replace(sig, new_sig); new_q.replace(sig, new_sig);
cell->set("\\Q", new_q); cell->set("\\Q", new_q);
} }
} }
}
static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
{ {
@ -170,13 +166,13 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only) static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only)
{ {
for (auto &cell_it : module->cells_) { for (auto cell : module->cells()) {
if (!design->selected(module, cell_it.second)) if (!design->selected(module, cell))
continue; continue;
if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
handle_wr_cell(module, cell_it.second); handle_wr_cell(module, cell);
if (!flag_wr_only && cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) if (!flag_wr_only && cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
handle_rd_cell(module, cell_it.second); handle_rd_cell(module, cell);
} }
} }
@ -212,9 +208,9 @@ struct MemoryDffPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (design->selected(mod_it.second)) if (design->selected(mod))
handle_module(design, mod_it.second, flag_wr_only); handle_module(design, mod, flag_wr_only);
} }
} MemoryDffPass; } MemoryDffPass;

23
passes/opt/opt_muxtree.cc
View file

@ -83,9 +83,8 @@ struct OptMuxtreeWorker
// .ctrl_sigs // .ctrl_sigs
// .input_sigs // .input_sigs
// .const_activated // .const_activated
for (auto &cell_it : module->cells_) for (auto cell : module->cells())
{ {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
{ {
RTLIL::SigSpec sig_a = cell->get("\\A"); RTLIL::SigSpec sig_a = cell->get("\\A");
@ -136,9 +135,9 @@ struct OptMuxtreeWorker
} }
} }
} }
for (auto &it : module->wires_) { for (auto wire : module->wires()) {
if (it.second->port_output) if (wire->port_output)
for (int idx : sig2bits(RTLIL::SigSpec(it.second))) for (int idx : sig2bits(RTLIL::SigSpec(wire)))
bit2info[idx].seen_non_mux = true; bit2info[idx].seen_non_mux = true;
} }
@ -423,16 +422,16 @@ struct OptMuxtreePass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
int total_count = 0; int total_count = 0;
for (auto &mod_it : design->modules_) { for (auto mod : design->modules()) {
if (!design->selected_whole_module(mod_it.first)) { if (!design->selected_whole_module(mod)) {
if (design->selected(mod_it.second)) if (design->selected(mod))
log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name)); log("Skipping module %s as it is only partially selected.\n", log_id(mod));
continue; continue;
} }
if (mod_it.second->processes.size() > 0) { if (mod->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", id2cstr(mod_it.second->name)); log("Skipping module %s as it contains processes.\n", log_id(mod));
} else { } else {
OptMuxtreeWorker worker(design, mod_it.second); OptMuxtreeWorker worker(design, mod);
total_count += worker.removed_count; total_count += worker.removed_count;
} }
} }

25
passes/proc/proc_arst.cc
View file

@ -33,20 +33,24 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
if (signal == ref) if (signal == ref)
return true; return true;
for (auto &cell_it : mod->cells_) { for (auto cell : mod->cells())
RTLIL::Cell *cell = cell_it.second; {
if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity); return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal) if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity); return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$logic_not" && cell->get("\\Y") == signal) { if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
polarity = !polarity; polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity); return check_signal(mod, cell->get("\\A"), ref, polarity);
} }
if (cell->type == "$not" && cell->get("\\Y") == signal) { if (cell->type == "$not" && cell->get("\\Y") == signal) {
polarity = !polarity; polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity); return check_signal(mod, cell->get("\\A"), ref, polarity);
} }
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) { if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) { if (cell->get("\\A").is_fully_const()) {
if (!cell->get("\\A").as_bool()) if (!cell->get("\\A").as_bool())
@ -59,6 +63,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
return check_signal(mod, cell->get("\\A"), ref, polarity); return check_signal(mod, cell->get("\\A"), ref, polarity);
} }
} }
if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) { if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) { if (cell->get("\\A").is_fully_const()) {
if (cell->get("\\A").as_bool()) if (cell->get("\\A").as_bool())
@ -236,14 +241,14 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (design->selected(mod_it.second)) { if (design->selected(mod)) {
SigMap assign_map(mod_it.second); SigMap assign_map(mod);
for (auto &proc_it : mod_it.second->processes) { for (auto &proc_it : mod->processes) {
if (!design->selected(mod_it.second, proc_it.second)) if (!design->selected(mod, proc_it.second))
continue; continue;
proc_arst(mod_it.second, proc_it.second, assign_map); proc_arst(mod, proc_it.second, assign_map);
if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0) if (global_arst.empty() || mod->wire(global_arst) == nullptr)
continue; continue;
std::vector<RTLIL::SigSig> arst_actions; std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc_it.second->syncs) for (auto sync : proc_it.second->syncs)
@ -266,7 +271,7 @@ struct ProcArstPass : public Pass {
if (!arst_actions.empty()) { if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule; RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
sync->signal = mod_it.second->wires_.at(global_arst); sync->signal = mod->wire(global_arst);
sync->actions = arst_actions; sync->actions = arst_actions;
proc_it.second->syncs.push_back(sync); proc_it.second->syncs.push_back(sync);
} }

16
passes/proc/proc_clean.cc
View file

@ -149,23 +149,23 @@ struct ProcCleanPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) { for (auto mod : design->modules()) {
std::vector<std::string> delme; std::vector<std::string> delme;
if (!design->selected(mod_it.second)) if (!design->selected(mod))
continue; continue;
for (auto &proc_it : mod_it.second->processes) { for (auto &proc_it : mod->processes) {
if (!design->selected(mod_it.second, proc_it.second)) if (!design->selected(mod, proc_it.second))
continue; continue;
proc_clean(mod_it.second, proc_it.second, total_count); proc_clean(mod, proc_it.second, total_count);
if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 && if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
proc_it.second->root_case.actions.size() == 0) { proc_it.second->root_case.actions.size() == 0) {
log("Removing empty process `%s.%s'.\n", mod_it.first.c_str(), proc_it.second->name.c_str()); log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
delme.push_back(proc_it.first); delme.push_back(proc_it.first);
} }
} }
for (auto &id : delme) { for (auto &id : delme) {
delete mod_it.second->processes[id]; delete mod->processes[id];
mod_it.second->processes.erase(id); mod->processes.erase(id);
} }
} }

12
passes/proc/proc_dff.cc
View file

@ -371,12 +371,12 @@ struct ProcDffPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (design->selected(mod_it.second)) { if (design->selected(mod)) {
ConstEval ce(mod_it.second); ConstEval ce(mod);
for (auto &proc_it : mod_it.second->processes) for (auto &proc_it : mod->processes)
if (design->selected(mod_it.second, proc_it.second)) if (design->selected(mod, proc_it.second))
proc_dff(mod_it.second, proc_it.second, ce); proc_dff(mod, proc_it.second, ce);
} }
} }
} ProcDffPass; } ProcDffPass;

10
passes/proc/proc_init.cc
View file

@ -101,11 +101,11 @@ struct ProcInitPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (design->selected(mod_it.second)) if (design->selected(mod))
for (auto &proc_it : mod_it.second->processes) for (auto &proc_it : mod->processes)
if (design->selected(mod_it.second, proc_it.second)) if (design->selected(mod, proc_it.second))
proc_init(mod_it.second, proc_it.second); proc_init(mod, proc_it.second);
} }
} ProcInitPass; } ProcInitPass;

10
passes/proc/proc_mux.cc
View file

@ -276,11 +276,11 @@ struct ProcMuxPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (design->selected(mod_it.second)) if (design->selected(mod))
for (auto &proc_it : mod_it.second->processes) for (auto &proc_it : mod->processes)
if (design->selected(mod_it.second, proc_it.second)) if (design->selected(mod, proc_it.second))
proc_mux(mod_it.second, proc_it.second); proc_mux(mod, proc_it.second);
} }
} ProcMuxPass; } ProcMuxPass;

10
passes/proc/proc_rmdead.cc
View file

@ -79,18 +79,18 @@ struct ProcRmdeadPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
int total_counter = 0; int total_counter = 0;
for (auto &mod_it : design->modules_) { for (auto mod : design->modules()) {
if (!design->selected(mod_it.second)) if (!design->selected(mod))
continue; continue;
for (auto &proc_it : mod_it.second->processes) { for (auto &proc_it : mod->processes) {
if (!design->selected(mod_it.second, proc_it.second)) if (!design->selected(mod, proc_it.second))
continue; continue;
int counter = 0; int counter = 0;
for (auto switch_it : proc_it.second->root_case.switches) for (auto switch_it : proc_it.second->root_case.switches)
proc_rmdead(switch_it, counter); proc_rmdead(switch_it, counter);
if (counter > 0) if (counter > 0)
log("Removed %d dead cases from process %s in module %s.\n", counter, log("Removed %d dead cases from process %s in module %s.\n", counter,
proc_it.first.c_str(), mod_it.first.c_str()); proc_it.first.c_str(), log_id(mod));
total_counter += counter; total_counter += counter;
} }
} }

20
passes/techmap/simplemap.cc
View file

@ -435,21 +435,19 @@ struct SimplemapPass : public Pass {
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers; std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers); simplemap_get_mappers(mappers);
for (auto &mod_it : design->modules_) { for (auto mod : design->modules()) {
if (!design->selected(mod_it.second)) if (!design->selected(mod))
continue; continue;
std::vector<RTLIL::Cell*> delete_cells; std::vector<RTLIL::Cell*> cells = mod->cells();
for (auto &cell_it : mod_it.second->cells_) { for (auto cell : cells) {
if (mappers.count(cell_it.second->type) == 0) if (mappers.count(cell->type) == 0)
continue; continue;
if (!design->selected(mod_it.second, cell_it.second)) if (!design->selected(mod, cell))
continue; continue;
log("Mapping %s.%s (%s).\n", RTLIL::id2cstr(mod_it.first), RTLIL::id2cstr(cell_it.first), RTLIL::id2cstr(cell_it.second->type)); log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
mappers.at(cell_it.second->type)(mod_it.second, cell_it.second); mappers.at(cell->type)(mod, cell);
delete_cells.push_back(cell_it.second); mod->remove(cell);
} }
for (auto c : delete_cells)
mod_it.second->remove(c);
} }
} }
} SimplemapPass; } SimplemapPass;

20
passes/techmap/techmap.cc
View file

@ -658,9 +658,9 @@ struct FlattenPass : public Pass {
RTLIL::Module *top_mod = NULL; RTLIL::Module *top_mod = NULL;
if (design->full_selection()) if (design->full_selection())
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (mod_it.second->get_bool_attribute("\\top")) if (mod->get_bool_attribute("\\top"))
top_mod = mod_it.second; top_mod = mod;
bool did_something = true; bool did_something = true;
std::set<RTLIL::Cell*> handled_cells; std::set<RTLIL::Cell*> handled_cells;
@ -670,8 +670,8 @@ struct FlattenPass : public Pass {
if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
did_something = true; did_something = true;
} else { } else {
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, true))
did_something = true; did_something = true;
} }
} }
@ -680,12 +680,12 @@ struct FlattenPass : public Pass {
if (top_mod != NULL) { if (top_mod != NULL) {
std::map<RTLIL::IdString, RTLIL::Module*> new_modules; std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
for (auto &mod_it : design->modules_) for (auto mod : design->modules())
if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) { if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) {
new_modules[mod_it.first] = mod_it.second; new_modules[mod->name] = mod;
} else { } else {
log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first)); log("Deleting now unused module %s.\n", log_id(mod));
delete mod_it.second; delete mod;
} }
design->modules_.swap(new_modules); design->modules_.swap(new_modules);
} }