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Using new obj iterator API in a few places

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This commit is contained in:
Clifford Wolf 2014-07-27 10:41:42 +02:00
parent 675cb93da9
commit 49f72421d5
10 changed files with 85 additions and 87 deletions
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25
passes/proc/proc_arst.cc
View file

@ -33,20 +33,24 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
if (signal == ref)
return true;
for (auto &cell_it : mod->cells_) {
RTLIL::Cell *cell = cell_it.second;
for (auto cell : mod->cells())
{
if (cell->type == "$reduce_or" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$reduce_bool" && cell->get("\\Y") == signal)
return check_signal(mod, cell->get("\\A"), ref, polarity);
if (cell->type == "$logic_not" && cell->get("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
}
if (cell->type == "$not" && cell->get("\\Y") == signal) {
polarity = !polarity;
return check_signal(mod, cell->get("\\A"), ref, polarity);
}
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (!cell->get("\\A").as_bool())
@ -59,6 +63,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp
return check_signal(mod, cell->get("\\A"), ref, polarity);
}
}
if ((cell->type == "$ne" || cell->type == "$nex") && cell->get("\\Y") == signal) {
if (cell->get("\\A").is_fully_const()) {
if (cell->get("\\A").as_bool())
@ -236,14 +241,14 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
SigMap assign_map(mod_it.second);
for (auto &proc_it : mod_it.second->processes) {
if (!design->selected(mod_it.second, proc_it.second))
for (auto mod : design->modules())
if (design->selected(mod)) {
SigMap assign_map(mod);
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
proc_arst(mod_it.second, proc_it.second, assign_map);
if (global_arst.empty() || mod_it.second->wires_.count(global_arst) == 0)
proc_arst(mod, proc_it.second, assign_map);
if (global_arst.empty() || mod->wire(global_arst) == nullptr)
continue;
std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc_it.second->syncs)
@ -266,7 +271,7 @@ struct ProcArstPass : public Pass {
if (!arst_actions.empty()) {
RTLIL::SyncRule *sync = new RTLIL::SyncRule;
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
sync->signal = mod_it.second->wires_.at(global_arst);
sync->signal = mod->wire(global_arst);
sync->actions = arst_actions;
proc_it.second->syncs.push_back(sync);
}

16
passes/proc/proc_clean.cc
View file

@ -149,23 +149,23 @@ struct ProcCleanPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules_) {
for (auto mod : design->modules()) {
std::vector<std::string> delme;
if (!design->selected(mod_it.second))
if (!design->selected(mod))
continue;
for (auto &proc_it : mod_it.second->processes) {
if (!design->selected(mod_it.second, proc_it.second))
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
proc_clean(mod_it.second, proc_it.second, total_count);
proc_clean(mod, proc_it.second, total_count);
if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
proc_it.second->root_case.actions.size() == 0) {
log("Removing empty process `%s.%s'.\n", mod_it.first.c_str(), proc_it.second->name.c_str());
log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
delme.push_back(proc_it.first);
}
}
for (auto &id : delme) {
delete mod_it.second->processes[id];
mod_it.second->processes.erase(id);
delete mod->processes[id];
mod->processes.erase(id);
}
}

12
passes/proc/proc_dff.cc
View file

@ -371,12 +371,12 @@ struct ProcDffPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
ConstEval ce(mod_it.second);
for (auto &proc_it : mod_it.second->processes)
if (design->selected(mod_it.second, proc_it.second))
proc_dff(mod_it.second, proc_it.second, ce);
for (auto mod : design->modules())
if (design->selected(mod)) {
ConstEval ce(mod);
for (auto &proc_it : mod->processes)
if (design->selected(mod, proc_it.second))
proc_dff(mod, proc_it.second, ce);
}
}
} ProcDffPass;

10
passes/proc/proc_init.cc
View file

@ -101,11 +101,11 @@ struct ProcInitPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &proc_it : mod_it.second->processes)
if (design->selected(mod_it.second, proc_it.second))
proc_init(mod_it.second, proc_it.second);
for (auto mod : design->modules())
if (design->selected(mod))
for (auto &proc_it : mod->processes)
if (design->selected(mod, proc_it.second))
proc_init(mod, proc_it.second);
}
} ProcInitPass;

10
passes/proc/proc_mux.cc
View file

@ -276,11 +276,11 @@ struct ProcMuxPass : public Pass {
extra_args(args, 1, design);
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &proc_it : mod_it.second->processes)
if (design->selected(mod_it.second, proc_it.second))
proc_mux(mod_it.second, proc_it.second);
for (auto mod : design->modules())
if (design->selected(mod))
for (auto &proc_it : mod->processes)
if (design->selected(mod, proc_it.second))
proc_mux(mod, proc_it.second);
}
} ProcMuxPass;

10
passes/proc/proc_rmdead.cc
View file

@ -79,18 +79,18 @@ struct ProcRmdeadPass : public Pass {
extra_args(args, 1, design);
int total_counter = 0;
for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
for (auto mod : design->modules()) {
if (!design->selected(mod))
continue;
for (auto &proc_it : mod_it.second->processes) {
if (!design->selected(mod_it.second, proc_it.second))
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
int counter = 0;
for (auto switch_it : proc_it.second->root_case.switches)
proc_rmdead(switch_it, counter);
if (counter > 0)
log("Removed %d dead cases from process %s in module %s.\n", counter,
proc_it.first.c_str(), mod_it.first.c_str());
proc_it.first.c_str(), log_id(mod));
total_counter += counter;
}
}