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https://github.com/YosysHQ/yosys
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Fix splitfanout: keep original cell, add new cells to driver db to fix net messup
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9ecb4e798e
commit
49d948d873
1 changed files with 24 additions and 9 deletions
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@ -101,11 +101,30 @@ struct SplitfanoutWorker
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log_debug("Splitting %s cell %s/%s into %d copies based on fanout\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
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log_debug("Splitting %s cell %s/%s into %d copies based on fanout\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
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int foi = 0;
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int foi = 0;
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cell->unsetPort(outport);
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cell->unsetPort(outport);
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int num_new_cells = GetSize(bit_users)-1;
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int bit_user_i = num_new_cells;
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for (auto bit_user : bit_users)
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for (auto bit_user : bit_users)
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{
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{
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// Create a new cell
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// Configure the driver cell
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IdString new_name = module->uniquify(cell->name.str());
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IdString new_name;
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Cell *new_cell = module->addCell(new_name, cell);
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Cell *new_cell;
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if (bit_user_i-- != 0) { // create a new cell
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new_name = module->uniquify(cell->name.str());
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new_cell = module->addCell(new_name, cell);
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// Add new cell to the bit_users_db
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for (auto conn : new_cell->connections()) {
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if (!new_cell->input(conn.first)) continue;
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit(sigmap(conn.second[i]));
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if (!bit_drivers_db.count(bit)) continue;
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bit_users_db[bit].insert(tuple<IdString,IdString,int>(new_cell->name,
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conn.first, i-std::get<2>(bit_drivers_db[bit])));
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}
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}
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} else { // if last cell, reuse the original cell
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new_name = cell->name;
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new_cell = cell;
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}
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// Connect the new cell to the user
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// Connect the new cell to the user
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if (std::get<1>(bit_user) == IdString()) { // is wire
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if (std::get<1>(bit_user) == IdString()) { // is wire
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@ -120,7 +139,6 @@ struct SplitfanoutWorker
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else {
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else {
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Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig));
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Wire *new_wire = module->addWire(NEW_ID, GetSize(outsig));
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Cell *target_cell = module->cell(std::get<0>(bit_user));
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Cell *target_cell = module->cell(std::get<0>(bit_user));
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if (!target_cell) continue; // cell might no longer exist
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SigSpec sig = target_cell->getPort(std::get<1>(bit_user));
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SigSpec sig = target_cell->getPort(std::get<1>(bit_user));
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sig.replace(std::get<2>(bit_user), new_wire);
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sig.replace(std::get<2>(bit_user), new_wire);
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module->cell(std::get<0>(bit_user))->setPort(std::get<1>(bit_user), sig);
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module->cell(std::get<0>(bit_user))->setPort(std::get<1>(bit_user), sig);
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@ -131,14 +149,11 @@ struct SplitfanoutWorker
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log_debug(" slice %d: %s => %s\n", foi++, log_id(new_name), log_signal(new_cell->getPort(outport)));
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log_debug(" slice %d: %s => %s\n", foi++, log_id(new_name), log_signal(new_cell->getPort(outport)));
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}
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}
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// Remove the original cell
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module->remove(cell);
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// Fix up ports
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// Fix up ports
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module->fixup_ports();
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module->fixup_ports();
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// Return the number of new cells created
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// Return the number of new cells created
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return GetSize(bit_users)-1;
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return num_new_cells;
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}
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}
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};
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};
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@ -153,7 +168,7 @@ struct SplitfanoutPass : public Pass {
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log("This command copies selected cells with >1 fanout into cells with fanout 1. It\n");
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log("This command copies selected cells with >1 fanout into cells with fanout 1. It\n");
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log("is effectively the opposite of the opt_merge pass.\n");
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log("is effectively the opposite of the opt_merge pass.\n");
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log("\n");
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log("\n");
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log("This command operates only on cells with 1 output and no \"bit split\" on that\n");
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log("This command operates only on cells with 1 output and no 'bit split' on that\n");
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log("output.\n");
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log("output.\n");
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log("\n");
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log("\n");
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}
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}
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