From 498cb79abe9b9239d5dcd5174185fc3bfd51261d Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 9 Mar 2026 20:18:56 +0100
Subject: [PATCH] async2sync: explain dffsr control signal variable polarity

---
 passes/sat/async2sync.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index 707343a5d..086dd5278 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -178,6 +178,9 @@ struct Async2syncPass : public Pass {
 								sig_clr = module->NotGate(NEW_ID, sig_clr);
 						}
 
+						// At this point, sig_set and sig_clr are now unconditionally
+						// active-high, and sig_clr_inv is inverted sig_clr
+
 						SigSpec set_and_clr;
 						if (!ff.is_fine)
 							set_and_clr = module->And(NEW_ID, sig_set, sig_clr);