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Improved attributes API and handling of "src" attributes

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This commit is contained in:
Clifford Wolf 2015-04-24 22:04:05 +02:00
parent 687f5a5b12
commit 49859393bb
7 changed files with 119 additions and 27 deletions
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40
kernel/rtlil.cc
View file

@ -161,6 +161,46 @@ std::string RTLIL::Const::decode_string() const
return string;
}
void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
{
attributes[id] = RTLIL::Const(1);
}
bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
{
if (attributes.count(id) == 0)
return false;
return attributes.at(id).as_bool();
}
void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
{
string attrval;
for (auto &s : data) {
if (!attrval.empty())
attrval += "|";
attrval += s;
}
attributes[id] = RTLIL::Const(attrval);
}
void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
{
pool<string> union_data = get_strpool_attribute(id);
union_data.insert(data.begin(), data.end());
if (!union_data.empty())
set_strpool_attribute(id, union_data);
}
pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
{
pool<string> data;
if (attributes.count(id) != 0)
for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
data.insert(s);
return data;
}
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)

41
kernel/rtlil.h
View file

@ -53,6 +53,7 @@ namespace RTLIL
};
struct Const;
struct AttrObject;
struct Selection;
struct Monitor;
struct Design;
@ -493,6 +494,17 @@ struct RTLIL::Const
}
};
struct RTLIL::AttrObject
{
dict<RTLIL::IdString, RTLIL::Const> attributes;
void set_bool_attribute(RTLIL::IdString id);
bool get_bool_attribute(RTLIL::IdString id) const;
void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
void add_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
pool<string> get_strpool_attribute(RTLIL::IdString id) const;
};
struct RTLIL::SigChunk
{
RTLIL::Wire *wire;
@ -849,18 +861,7 @@ struct RTLIL::Design
std::vector<RTLIL::Module*> selected_whole_modules_warn() const;
};
#define RTLIL_ATTRIBUTE_MEMBERS \
dict<RTLIL::IdString, RTLIL::Const> attributes; \
void set_bool_attribute(RTLIL::IdString id) { \
attributes[id] = RTLIL::Const(1); \
} \
bool get_bool_attribute(RTLIL::IdString id) const { \
if (attributes.count(id) == 0) \
return false; \
return attributes.at(id).as_bool(); \
}
struct RTLIL::Module
struct RTLIL::Module : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
@ -884,7 +885,6 @@ public:
pool<RTLIL::IdString> avail_parameters;
dict<RTLIL::IdString, RTLIL::Memory*> memories;
dict<RTLIL::IdString, RTLIL::Process*> processes;
RTLIL_ATTRIBUTE_MEMBERS
Module();
virtual ~Module();
@ -1095,7 +1095,7 @@ public:
RTLIL::SigBit Oai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d);
};
struct RTLIL::Wire
struct RTLIL::Wire : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
@ -1115,10 +1115,9 @@ public:
RTLIL::IdString name;
int width, start_offset, port_id;
bool port_input, port_output, upto;
RTLIL_ATTRIBUTE_MEMBERS
};
struct RTLIL::Memory
struct RTLIL::Memory : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
@ -1127,10 +1126,9 @@ struct RTLIL::Memory
RTLIL::IdString name;
int width, start_offset, size;
RTLIL_ATTRIBUTE_MEMBERS
};
struct RTLIL::Cell
struct RTLIL::Cell : public RTLIL::AttrObject
{
unsigned int hashidx_;
unsigned int hash() const { return hashidx_; }
@ -1150,7 +1148,6 @@ public:
RTLIL::IdString type;
dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
dict<RTLIL::IdString, RTLIL::Const> parameters;
RTLIL_ATTRIBUTE_MEMBERS
// access cell ports
bool hasPort(RTLIL::IdString portname) const;
@ -1195,10 +1192,9 @@ struct RTLIL::CaseRule
RTLIL::CaseRule *clone() const;
};
struct RTLIL::SwitchRule
struct RTLIL::SwitchRule : public RTLIL::AttrObject
{
RTLIL::SigSpec signal;
RTLIL_ATTRIBUTE_MEMBERS
std::vector<RTLIL::CaseRule*> cases;
~SwitchRule();
@ -1217,10 +1213,9 @@ struct RTLIL::SyncRule
RTLIL::SyncRule *clone() const;
};
struct RTLIL::Process
struct RTLIL::Process : public RTLIL::AttrObject
{
RTLIL::IdString name;
RTLIL_ATTRIBUTE_MEMBERS
RTLIL::CaseRule root_case;
std::vector<RTLIL::SyncRule*> syncs;

20
kernel/yosys.cc
View file

@ -209,6 +209,26 @@ std::string next_token(std::string &text, const char *sep, bool long_strings)
return token;
}
std::vector<std::string> split_tokens(const std::string &text, const char *sep)
{
std::vector<std::string> tokens;
std::string current_token;
for (char c : text) {
if (strchr(sep, c)) {
if (!current_token.empty()) {
tokens.push_back(current_token);
current_token.clear();
}
} else
current_token += c;
}
if (!current_token.empty()) {
tokens.push_back(current_token);
current_token.clear();
}
return tokens;
}
// this is very similar to fnmatch(). the exact rules used by this
// function are:
//

1
kernel/yosys.h
View file

@ -205,6 +205,7 @@ std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
std::string vstringf(const char *fmt, va_list ap);
int readsome(std::istream &f, char *s, int n);
std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false);
std::vector<std::string> split_tokens(const std::string &text, const char *sep = " \t\r\n");
bool patmatch(const char *pattern, const char *string);
int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
std::string make_temp_file(std::string template_str = "/tmp/yosys_XXXXXX");