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Improved attributes API and handling of "src" attributes

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Clifford Wolf 2015-04-24 22:04:05 +02:00
parent 687f5a5b12
commit 49859393bb
7 changed files with 119 additions and 27 deletions
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@ -300,6 +300,11 @@ Verilog Attributes and non-standard features
with "-top". Other commands, such as "flatten" and various backends
use this attribute to determine the top module.
- The "src" attribute is set on cells and wires created by to the string
"<hdl-file-name>:<line-number>" by the HDL front-end and is then carried
through the synthesis. When entities are combined, a new |-separated
string is created that contains all the string from the original entities.
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset