diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
index 22ff63642..4572bb976 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
+++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
@@ -3,10 +3,11 @@ module TB(input clk);
 parameter ADDRESS_WIDTH = 10;
 parameter DATA_WIDTH = 36;
 parameter VECTORLEN = 16;
+localparam MAX_WIDTH = 36;
 
 reg rce_a_testvector [VECTORLEN-1:0];
 reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0];
-reg [DATA_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
+reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0];
 
 reg wce_a_testvector [VECTORLEN-1:0];
 reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0];
@@ -14,7 +15,7 @@ reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0];
 
 reg rce_b_testvector [VECTORLEN-1:0];
 reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0];
-reg [DATA_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
+reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0];
 
 reg wce_b_testvector [VECTORLEN-1:0];
 reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0];
@@ -43,7 +44,7 @@ end
 
 wire rce_a = rce_a_testvector[i];
 wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i];
-wire [DATA_WIDTH-1:0] rq_a_e = rq_a_expected[i];
+wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i];
 wire [DATA_WIDTH-1:0] rq_a;
 
 wire wce_a = wce_a_testvector[i];
@@ -52,7 +53,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i];
 
 wire rce_b = rce_b_testvector[i];
 wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i];
-wire [DATA_WIDTH-1:0] rq_b_e = rq_b_expected[i];
+wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i];
 wire [DATA_WIDTH-1:0] rq_b;
 
 wire wce_b = wce_b_testvector[i];