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fix compile bug

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This commit is contained in:
treelin611 2026-05-20 15:12:40 +08:00
parent 3c5ba1337e
commit 4973d135a2
1 changed files with 2 additions and 2 deletions
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4
techlibs/rapidflex/src/rf_new_dsp.pmg
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@ -368,7 +368,7 @@ match ff
filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ
@ -406,7 +406,7 @@ match ff
filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
filter port(ff, \D).extract(offset, GetSize(argD)) == argD
filter clock == SigBit() || port(ff, \CLK) == clock
filter clock == SigBit() || port(ff, \CLK)[0] == clock
endmatch
code argQ