mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-13 09:31:16 +00:00
Don't reset the hash when unpacking, instead clear the hash whenever bits are modified
This commit is contained in:
parent
aa4a0fe815
commit
4939484840
2 changed files with 20 additions and 3 deletions
|
|
@ -4733,7 +4733,6 @@ void RTLIL::SigSpec::unpack() const
|
|||
that->bits_.emplace_back(c, i);
|
||||
|
||||
that->chunks_.clear();
|
||||
that->hash_ = 0;
|
||||
}
|
||||
|
||||
void RTLIL::SigSpec::updhash() const
|
||||
|
|
@ -4765,6 +4764,7 @@ void RTLIL::SigSpec::sort()
|
|||
unpack();
|
||||
cover("kernel.rtlil.sigspec.sort");
|
||||
std::sort(bits_.begin(), bits_.end());
|
||||
hash_ = 0;
|
||||
}
|
||||
|
||||
void RTLIL::SigSpec::sort_and_unify()
|
||||
|
|
@ -4781,6 +4781,7 @@ void RTLIL::SigSpec::sort_and_unify()
|
|||
unique_bits.erase(last, unique_bits.end());
|
||||
|
||||
*this = unique_bits;
|
||||
hash_ = 0;
|
||||
}
|
||||
|
||||
void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec &with)
|
||||
|
|
@ -4812,6 +4813,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
|
|||
other->bits_[j] = with.bits_[it->second];
|
||||
}
|
||||
}
|
||||
other->hash_ = 0;
|
||||
|
||||
other->check();
|
||||
}
|
||||
|
|
@ -4837,6 +4839,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
|
|||
if (it != rules.end())
|
||||
other->bits_[i] = it->second;
|
||||
}
|
||||
other->hash_ = 0;
|
||||
|
||||
other->check();
|
||||
}
|
||||
|
|
@ -4862,6 +4865,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
|
|||
if (it != rules.end())
|
||||
other->bits_[i] = it->second;
|
||||
}
|
||||
other->hash_ = 0;
|
||||
|
||||
other->check();
|
||||
}
|
||||
|
|
@ -4888,6 +4892,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
|
|||
if (other != NULL) {
|
||||
log_assert(size() == other->size());
|
||||
other->unpack();
|
||||
other->hash_ = 0;
|
||||
}
|
||||
|
||||
for (int i = GetSize(bits_) - 1; i >= 0; i--)
|
||||
|
|
@ -4907,6 +4912,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
|
|||
break;
|
||||
}
|
||||
}
|
||||
hash_ = 0;
|
||||
|
||||
check();
|
||||
}
|
||||
|
|
@ -4934,6 +4940,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
|
|||
if (other != NULL) {
|
||||
log_assert(size() == other->size());
|
||||
other->unpack();
|
||||
other->hash_ = 0;
|
||||
}
|
||||
|
||||
for (int i = GetSize(bits_) - 1; i >= 0; i--) {
|
||||
|
|
@ -4946,6 +4953,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
|
|||
}
|
||||
}
|
||||
}
|
||||
hash_ = 0;
|
||||
|
||||
check();
|
||||
}
|
||||
|
|
@ -4962,6 +4970,7 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
|
|||
if (other != NULL) {
|
||||
log_assert(size() == other->size());
|
||||
other->unpack();
|
||||
other->hash_ = 0;
|
||||
}
|
||||
|
||||
for (int i = GetSize(bits_) - 1; i >= 0; i--) {
|
||||
|
|
@ -4974,6 +4983,7 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
|
|||
}
|
||||
}
|
||||
}
|
||||
hash_ = 0;
|
||||
|
||||
check();
|
||||
}
|
||||
|
|
@ -4990,6 +5000,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *
|
|||
if (other != NULL) {
|
||||
log_assert(size() == other->size());
|
||||
other->unpack();
|
||||
other->hash_ = 0;
|
||||
}
|
||||
|
||||
for (int i = GetSize(bits_) - 1; i >= 0; i--) {
|
||||
|
|
@ -5002,6 +5013,7 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::Wire*> &pattern, RTLIL::SigSpec *
|
|||
}
|
||||
}
|
||||
}
|
||||
hash_ = 0;
|
||||
|
||||
check();
|
||||
}
|
||||
|
|
@ -5089,6 +5101,7 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
|
|||
bits_.at(offset + i) = bit;
|
||||
++i;
|
||||
}
|
||||
hash_ = 0;
|
||||
|
||||
check();
|
||||
}
|
||||
|
|
@ -5132,6 +5145,7 @@ void RTLIL::SigSpec::remove_const()
|
|||
width_ = bits_.size();
|
||||
}
|
||||
|
||||
hash_ = 0;
|
||||
check();
|
||||
}
|
||||
|
||||
|
|
@ -5148,6 +5162,7 @@ void RTLIL::SigSpec::remove(int offset, int length)
|
|||
bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
|
||||
width_ = bits_.size();
|
||||
|
||||
hash_ = 0;
|
||||
check();
|
||||
}
|
||||
|
||||
|
|
@ -5194,6 +5209,7 @@ void RTLIL::SigSpec::rewrite_wires(std::function<void(RTLIL::Wire*& wire)> rewri
|
|||
for (RTLIL::SigChunk &chunk : chunks_)
|
||||
if (chunk.wire != nullptr)
|
||||
rewrite(chunk.wire);
|
||||
hash_ = 0;
|
||||
}
|
||||
|
||||
void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
|
||||
|
|
@ -5229,6 +5245,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal)
|
|||
}
|
||||
|
||||
width_ += signal.size();
|
||||
hash_ = 0;
|
||||
check();
|
||||
}
|
||||
|
||||
|
|
@ -5260,6 +5277,7 @@ void RTLIL::SigSpec::append(const RTLIL::SigBit &bit)
|
|||
}
|
||||
|
||||
width_++;
|
||||
hash_ = 0;
|
||||
check();
|
||||
}
|
||||
|
||||
|
|
@ -5277,7 +5295,6 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
|
|||
while (size() < width)
|
||||
append(padding);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
|
||||
|
|
|
|||
|
|
@ -1369,7 +1369,7 @@ public:
|
|||
inline int size() const { return width_; }
|
||||
inline bool empty() const { return size() == 0; }
|
||||
|
||||
inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); }
|
||||
inline RTLIL::SigBit &operator[](int index) { inline_unpack(); hash_ = 0; return bits_.at(index); }
|
||||
inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); }
|
||||
|
||||
inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; }
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue