Asymmetric port ram tests with Xilinx

Uses verilog code from User Guide 901 (2021.1)

tests/arch/xilinx/asym_ram_sdp.ys

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+# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
+
+# w4b | r16b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w8b | r16b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w4b | r32b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w16b | r4b
+design -reset
+read_verilog asym_ram_sdp_write_wider.v
+synth_xilinx -top asym_ram_sdp_write_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w16b | r8b
+design -reset
+read_verilog asym_ram_sdp_write_wider.v
+chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_write_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w32b | r4b
+design -reset
+read_verilog asym_ram_sdp_write_wider.v
+chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_write_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+
+# w4b | r24b
+design -reset
+read_verilog asym_ram_sdp_read_wider.v
+chparam -set SIZEA 768
+chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider
+synth_xilinx -top asym_ram_sdp_read_wider -noiopad
+select -assert-count 1 t:RAMB18E1
+

tests/arch/xilinx/asym_ram_sdp_read_wider.v

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+// Asymmetric port RAM
+// Read Wider than Write. Read Statement in loop
+//asym_ram_sdp_read_wider.v
+module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB);
+	parameter WIDTHA = 4;
+	parameter SIZEA = 1024;
+	parameter ADDRWIDTHA = 10;
+	
+	parameter WIDTHB = 16;
+	parameter SIZEB = 256;
+	parameter ADDRWIDTHB = 8;
+
+	input clkA;
+	input clkB;
+	input weA;
+	input enaA, enaB;
+	input [ADDRWIDTHA-1:0] addrA;
+	input [ADDRWIDTHB-1:0] addrB;
+	input [WIDTHA-1:0] diA;
+	output [WIDTHB-1:0] doB;
+
+	`define max(a,b) {(a) > (b) ? (a) : (b)}
+	`define min(a,b) {(a) < (b) ? (a) : (b)}
+
+	function integer log2;
+	input integer value;
+	reg [31:0] shifted;
+	integer res;
+	begin
+		if (value < 2)
+			log2 = value;
+		else
+		begin
+			shifted = value-1;
+			for (res=0; shifted>0; res=res+1)
+				shifted = shifted>>1;
+			log2 = res;
+		end
+	end
+	endfunction
+
+	localparam maxSIZE = `max(SIZEA, SIZEB);
+	localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+	localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+	localparam RATIO = maxWIDTH / minWIDTH;
+	localparam log2RATIO = log2(RATIO);
+
+	reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+	reg [WIDTHB-1:0] readB;
+
+	always @(posedge clkA)
+	begin
+		if (enaA) begin
+			if (weA)
+				RAM[addrA] <= diA;
+		end
+	end
+
+	always @(posedge clkB)
+	begin : ramread
+		integer i;
+		reg [log2RATIO-1:0] lsbaddr;
+		if (enaB) begin
+			for (i = 0; i < RATIO; i = i+1) begin
+				lsbaddr = i;
+				readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
+			end
+		end
+	end
+	assign doB = readB;
+endmodule

tests/arch/xilinx/asym_ram_sdp_write_wider.v

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+// Asymmetric port RAM
+// Write wider than Read. Write Statement in a loop.
+// asym_ram_sdp_write_wider.v
+module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB);
+	parameter WIDTHB = 4;
+	parameter SIZEB = 1024;
+	parameter ADDRWIDTHB = 10;
+
+	parameter WIDTHA = 16;
+	parameter SIZEA = 256;
+	parameter ADDRWIDTHA = 8;
+
+	input clkA;
+	input clkB;
+	input weA;
+	input enaA, enaB;
+	input [ADDRWIDTHA-1:0] addrA;
+	input [ADDRWIDTHB-1:0] addrB;
+	input [WIDTHA-1:0] diA;
+	output [WIDTHB-1:0] doB;
+
+	`define max(a,b) {(a) > (b) ? (a) : (b)}
+	`define min(a,b) {(a) < (b) ? (a) : (b)}
+
+	function integer log2;
+	input integer value;
+	reg [31:0] shifted;
+	integer res;
+	begin
+		if (value < 2)
+			log2 = value;
+		else
+		begin
+			shifted = value-1;
+			for (res=0; shifted>0; res=res+1)
+				shifted = shifted>>1;
+			log2 = res;
+		end
+	end
+	endfunction
+
+	localparam maxSIZE = `max(SIZEA, SIZEB);
+	localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+	localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+	localparam RATIO = maxWIDTH / minWIDTH;
+	localparam log2RATIO = log2(RATIO);
+
+	reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+	reg [WIDTHB-1:0] readB;
+
+	always @(posedge clkB) begin
+		if (enaB) begin
+			readB <= RAM[addrB];
+		end
+	end
+	assign doB = readB;
+
+	always @(posedge clkA)
+	begin : ramwrite
+		integer i;
+		reg [log2RATIO-1:0] lsbaddr;
+		for (i=0; i< RATIO; i= i+ 1) begin : write1
+			lsbaddr = i;
+			if (enaA) begin
+				if (weA)
+					RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
+			end
+		end
+	end
+endmodule