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Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
This commit is contained in:
Eddie Hung
GitHub
commit
48f3f5213e
11 changed files with 1833 additions and 1410 deletions
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@ -93,7 +93,6 @@ struct XAigerWriter
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dict<SigBit, int> ordered_outputs;
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vector<Cell*> box_list;
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dict<IdString, std::vector<IdString>> box_ports;
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int mkgate(int a0, int a1)
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{
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@ -157,7 +156,6 @@ struct XAigerWriter
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if (wire->get_bool_attribute(ID::keep))
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sigmap.add(wire);
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for (auto wire : module->wires())
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for (int i = 0; i < GetSize(wire); i++)
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{
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@ -175,108 +173,96 @@ struct XAigerWriter
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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if (wire->port_input)
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bool keep = wire->get_bool_attribute(ID::keep);
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if (wire->port_input || keep)
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input_bits.insert(bit);
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if (wire->port_output) {
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if (wire->port_output || keep) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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}
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// TODO: Speed up toposort -- ultimately we care about
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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unused_bits.erase(A);
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undriven_bits.erase(Y);
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not_map[Y] = A;
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit B = sigmap(cell->getPort("\\B").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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unused_bits.erase(A);
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unused_bits.erase(B);
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undriven_bits.erase(Y);
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and_map[Y] = make_pair(A, B);
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_users[B].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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continue;
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}
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if (cell->type == "$__ABC9_FF_" &&
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// The presence of an abc9_mergeability attribute indicates
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// that we do want to pass this flop to ABC
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cell->attributes.count("\\abc9_mergeability"))
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{
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SigBit D = sigmap(cell->getPort("\\D").as_bit());
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SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
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log_assert(r.second);
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continue;
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}
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dict<IdString,dict<IdString,int>> arrival_cache;
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for (auto cell : module->cells()) {
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module) {
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bool abc9_box = inst_module->attributes.count("\\abc9_box_id");
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bool abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
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if (abc9_box && cell->get_bool_attribute("\\abc9_keep"))
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abc9_box = false;
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if (!cell->has_keep_attr()) {
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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unused_bits.erase(A);
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undriven_bits.erase(Y);
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not_map[Y] = A;
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continue;
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}
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit B = sigmap(cell->getPort("\\B").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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unused_bits.erase(A);
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unused_bits.erase(B);
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undriven_bits.erase(Y);
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and_map[Y] = make_pair(A, B);
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continue;
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}
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if (abc9_box) {
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_input && !port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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if (cell->type == "$__ABC9_FF_" &&
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// The presence of an abc9_mergeability attribute indicates
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// that we do want to pass this flop to ABC
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cell->attributes.count("\\abc9_mergeability"))
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{
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SigBit D = sigmap(cell->getPort("\\D").as_bit());
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SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
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log_assert(r.second);
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if (input_bits.erase(Q))
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log_assert(Q.wire->attributes.count(ID::keep));
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continue;
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}
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if (inst_module) {
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bool abc9_flop = false;
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auto it = cell->attributes.find("\\abc9_box_seq");
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if (it != cell->attributes.end()) {
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int abc9_box_seq = it->second.as_int();
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if (GetSize(box_list) <= abc9_box_seq)
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box_list.resize(abc9_box_seq+1);
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box_list[abc9_box_seq] = cell;
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// Only flop boxes may have arrival times
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abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
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if (!abc9_flop)
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continue;
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}
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if (port_wire->port_output) {
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int arrival = 0;
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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auto &cell_arrivals = arrival_cache[cell->type];
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for (const auto &conn : cell->connections()) {
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auto r = cell_arrivals.insert(conn.first);
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auto &arrival = r.first->second;
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if (r.second) {
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auto port_wire = inst_module->wire(conn.first);
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if (port_wire->port_output) {
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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}
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}
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}
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if (arrival)
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for (auto bit : sigmap(conn.second))
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arrival_times[bit] = arrival;
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}
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}
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if (abc9_box) {
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abc9_box_seen = true;
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toposort.node(cell->name);
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continue;
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if (abc9_flop)
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continue;
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}
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}
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@ -293,6 +279,9 @@ struct XAigerWriter
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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// Do not add as PO if bit is already a PI
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if (input_bits.count(b))
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continue;
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if (!w->port_output || !cell_known) {
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SigBit I = sigmap(b);
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if (I != b)
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@ -305,138 +294,54 @@ struct XAigerWriter
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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if (abc9_box_seen) {
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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dict<IdString, std::vector<IdString>> box_ports;
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for (auto cell : box_list) {
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log_assert(cell);
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#if 0
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toposort.analyze_loops = true;
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#endif
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bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
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#if 0
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unsigned i = 0;
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for (auto &it : toposort.loops) {
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log(" loop %d\n", i++);
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for (auto cell_name : it) {
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auto cell = module->cell(cell_name);
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log_assert(cell);
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log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
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}
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}
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#endif
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log_assert(no_loops);
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RTLIL::Module* box_module = module->design->module(cell->type);
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log_assert(box_module);
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log_assert(box_module->attributes.count("\\abc9_box_id"));
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for (auto cell_name : toposort.sorted) {
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RTLIL::Cell *cell = module->cell(cell_name);
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log_assert(cell);
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RTLIL::Module* box_module = module->design->module(cell->type);
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if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
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continue;
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bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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carry_in = port_name;
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}
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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carry_out = port_name;
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}
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}
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else
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r.first->second.push_back(port_name);
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}
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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// Fully pad all unused input connections of this box cell with S0
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// Fully pad all undriven output connections of this box cell with anonymous wires
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for (auto port_name : r.first->second) {
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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// since ABC requires it this way
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IdString carry_in, carry_out;
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for (const auto &port_name : box_module->ports) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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auto it = cell->connections_.find(port_name);
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if (w->port_input) {
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RTLIL::SigSpec rhs;
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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if (w->get_bool_attribute("\\abc9_carry")) {
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if (w->port_input) {
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if (carry_in != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
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carry_in = port_name;
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}
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else {
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rhs = RTLIL::SigSpec(State::S0, GetSize(w));
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cell->setPort(port_name, rhs);
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}
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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b = State::S0;
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else if (I != b) {
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if (I == RTLIL::Sx)
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alias_map[b] = State::S0;
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else
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alias_map[b] = I;
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}
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co_bits.emplace_back(b);
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unused_bits.erase(I);
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}
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}
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if (w->port_output) {
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RTLIL::SigSpec rhs;
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auto it = cell->connections_.find(port_name);
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if (it != cell->connections_.end()) {
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if (GetSize(it->second) < GetSize(w))
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it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
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rhs = it->second;
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}
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else {
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Wire *wire = module->addWire(NEW_ID, GetSize(w));
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if (blackbox)
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wire->set_bool_attribute(ID(abc9_padding));
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rhs = wire;
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cell->setPort(port_name, rhs);
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}
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for (const auto &b : rhs.bits()) {
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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ci_bits.emplace_back(b);
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undriven_bits.erase(O);
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if (w->port_output) {
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if (carry_out != IdString())
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log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
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carry_out = port_name;
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}
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}
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else
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r.first->second.push_back(port_name);
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}
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// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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if (rhs.empty())
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log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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if (carry_in != IdString() && carry_out == IdString())
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log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
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if (carry_in == IdString() && carry_out != IdString())
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log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
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if (carry_in != IdString()) {
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r.first->second.push_back(carry_in);
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r.first->second.push_back(carry_out);
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}
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}
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for (auto port_name : r.first->second) {
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auto w = box_module->wire(port_name);
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log_assert(w);
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auto rhs = cell->connections_.at(port_name, SigSpec());
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rhs.append(Const(State::Sx, GetSize(w)-GetSize(rhs)));
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if (w->port_input)
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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@ -450,12 +355,41 @@ struct XAigerWriter
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co_bits.emplace_back(b);
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unused_bits.erase(I);
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}
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}
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box_list.emplace_back(cell);
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if (w->port_output)
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for (const auto &b : rhs) {
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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ci_bits.emplace_back(b);
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undriven_bits.erase(O);
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// If PI and CI, then must be a (* keep *) wire
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if (input_bits.erase(O)) {
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log_assert(output_bits.count(O));
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log_assert(O.wire->get_bool_attribute(ID::keep));
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}
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}
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}
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// TODO: Free memory from toposort, bit_drivers, bit_users
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// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
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if (rhs.empty())
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log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
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for (auto b : rhs) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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b = State::S0;
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else if (I != b) {
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||||
if (I == RTLIL::Sx)
|
||||
alias_map[b] = State::S0;
|
||||
else
|
||||
alias_map[b] = I;
|
||||
}
|
||||
co_bits.emplace_back(b);
|
||||
unused_bits.erase(I);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (auto bit : input_bits)
|
||||
|
|
@ -501,6 +435,10 @@ struct XAigerWriter
|
|||
|
||||
for (auto &bit : ci_bits) {
|
||||
aig_m++, aig_i++;
|
||||
// 1'bx may exist here due to a box output
|
||||
// that has been padded to its full width
|
||||
if (bit == State::Sx)
|
||||
continue;
|
||||
log_assert(!aig_map.count(bit));
|
||||
aig_map[bit] = 2*aig_m;
|
||||
}
|
||||
|
|
@ -512,7 +450,27 @@ struct XAigerWriter
|
|||
|
||||
for (const auto &bit : output_bits) {
|
||||
ordered_outputs[bit] = aig_o++;
|
||||
aig_outputs.push_back(bit2aig(bit));
|
||||
int aig;
|
||||
// Unlike bit2aig() which checks aig_map first, for
|
||||
// inout/keep bits, since aig_map will point to
|
||||
// the PI, first attempt to find the NOT/AND driver
|
||||
// before resorting to an aig_map lookup (which
|
||||
// could be another PO)
|
||||
if (input_bits.count(bit)) {
|
||||
if (not_map.count(bit)) {
|
||||
aig = bit2aig(not_map.at(bit)) ^ 1;
|
||||
} else if (and_map.count(bit)) {
|
||||
auto args = and_map.at(bit);
|
||||
int a0 = bit2aig(args.first);
|
||||
int a1 = bit2aig(args.second);
|
||||
aig = mkgate(a0, a1);
|
||||
}
|
||||
else
|
||||
aig = aig_map.at(bit);
|
||||
}
|
||||
else
|
||||
aig = bit2aig(bit);
|
||||
aig_outputs.push_back(aig);
|
||||
}
|
||||
|
||||
for (auto &i : ff_bits) {
|
||||
|
|
@ -612,106 +570,41 @@ struct XAigerWriter
|
|||
// write_o_buffer(0);
|
||||
|
||||
if (!box_list.empty() || !ff_bits.empty()) {
|
||||
RTLIL::Module *holes_module = module->design->addModule("$__holes__");
|
||||
log_assert(holes_module);
|
||||
dict<IdString, std::tuple<int,int,int>> cell_cache;
|
||||
|
||||
dict<IdString, std::tuple<Cell*,int,int,int>> cell_cache;
|
||||
|
||||
int port_id = 1;
|
||||
int box_count = 0;
|
||||
for (auto cell : box_list) {
|
||||
RTLIL::Module* orig_box_module = module->design->module(cell->type);
|
||||
log_assert(orig_box_module);
|
||||
IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
|
||||
RTLIL::Module* box_module = module->design->module(derived_name);
|
||||
log_assert(cell);
|
||||
|
||||
auto r = cell_cache.insert(derived_name);
|
||||
RTLIL::Module* box_module = module->design->module(cell->type);
|
||||
log_assert(box_module);
|
||||
|
||||
auto r = cell_cache.insert(cell->type);
|
||||
auto &v = r.first->second;
|
||||
if (r.second) {
|
||||
if (box_module->has_processes())
|
||||
Pass::call_on_module(module->design, box_module, "proc");
|
||||
|
||||
int box_inputs = 0, box_outputs = 0;
|
||||
if (box_module->get_bool_attribute("\\whitebox")) {
|
||||
auto holes_cell = holes_module->addCell(cell->name, derived_name);
|
||||
for (auto port_name : box_ports.at(cell->type)) {
|
||||
RTLIL::Wire *w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
log_assert(!w->port_input || !w->port_output);
|
||||
auto &conn = holes_cell->connections_[port_name];
|
||||
if (w->port_input) {
|
||||
for (int i = 0; i < GetSize(w); i++) {
|
||||
box_inputs++;
|
||||
RTLIL::Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
|
||||
if (!holes_wire) {
|
||||
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
|
||||
holes_wire->port_input = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
}
|
||||
conn.append(holes_wire);
|
||||
}
|
||||
}
|
||||
else if (w->port_output) {
|
||||
box_outputs += GetSize(w);
|
||||
conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
|
||||
}
|
||||
}
|
||||
|
||||
// For flops only, create an extra 1-bit input that drives a new wire
|
||||
// called "<cell>.abc9_ff.Q" that is used below
|
||||
if (box_module->get_bool_attribute("\\abc9_flop")) {
|
||||
box_inputs++;
|
||||
Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
|
||||
if (!holes_wire) {
|
||||
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
|
||||
holes_wire->port_input = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
}
|
||||
Wire *Q = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
|
||||
holes_module->connect(Q, holes_wire);
|
||||
}
|
||||
|
||||
std::get<0>(v) = holes_cell;
|
||||
}
|
||||
else {
|
||||
for (auto port_name : box_ports.at(cell->type)) {
|
||||
RTLIL::Wire *w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
log_assert(!w->port_input || !w->port_output);
|
||||
if (w->port_input)
|
||||
box_inputs += GetSize(w);
|
||||
else if (w->port_output)
|
||||
box_outputs += GetSize(w);
|
||||
}
|
||||
log_assert(std::get<0>(v) == nullptr);
|
||||
for (auto port_name : box_module->ports) {
|
||||
RTLIL::Wire *w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
if (w->port_input)
|
||||
box_inputs += GetSize(w);
|
||||
if (w->port_output)
|
||||
box_outputs += GetSize(w);
|
||||
}
|
||||
|
||||
std::get<1>(v) = box_inputs;
|
||||
std::get<2>(v) = box_outputs;
|
||||
std::get<3>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
|
||||
}
|
||||
|
||||
auto holes_cell = std::get<0>(v);
|
||||
for (auto port_name : box_ports.at(cell->type)) {
|
||||
RTLIL::Wire *w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
if (!w->port_output)
|
||||
continue;
|
||||
Wire *holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(port_name)), GetSize(w));
|
||||
holes_wire->port_output = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
if (holes_cell) // whitebox
|
||||
holes_module->connect(holes_wire, holes_cell->getPort(port_name));
|
||||
else // blackbox
|
||||
holes_module->connect(holes_wire, Const(State::S0, GetSize(w)));
|
||||
// For flops only, create an extra 1-bit input that drives a new wire
|
||||
// called "<cell>.abc9_ff.Q" that is used below
|
||||
if (box_module->get_bool_attribute("\\abc9_flop"))
|
||||
box_inputs++;
|
||||
|
||||
std::get<0>(v) = box_inputs;
|
||||
std::get<1>(v) = box_outputs;
|
||||
std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
|
||||
}
|
||||
|
||||
write_h_buffer(std::get<0>(v));
|
||||
write_h_buffer(std::get<1>(v));
|
||||
write_h_buffer(std::get<2>(v));
|
||||
write_h_buffer(std::get<3>(v));
|
||||
write_h_buffer(box_count++);
|
||||
}
|
||||
|
||||
|
|
@ -759,82 +652,17 @@ struct XAigerWriter
|
|||
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
|
||||
f.write(buffer_str.data(), buffer_str.size());
|
||||
|
||||
RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
|
||||
if (holes_module) {
|
||||
log_push();
|
||||
|
||||
// NB: fixup_ports() will sort ports by name
|
||||
//holes_module->fixup_ports();
|
||||
holes_module->check();
|
||||
|
||||
// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
|
||||
// since boxes may contain parameters in which case `flatten` would have
|
||||
// created a new $paramod ...
|
||||
Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
|
||||
|
||||
SigMap holes_sigmap(holes_module);
|
||||
|
||||
dict<SigSpec, SigSpec> replace;
|
||||
for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
|
||||
auto cell = it->second;
|
||||
if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
|
||||
"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
|
||||
SigBit D = cell->getPort("\\D");
|
||||
SigBit Q = cell->getPort("\\Q");
|
||||
// Remove the $_DFF_* cell from what needs to be a combinatorial box
|
||||
it = holes_module->cells_.erase(it);
|
||||
Wire *port;
|
||||
if (GetSize(Q.wire) == 1)
|
||||
port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
|
||||
else
|
||||
port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
|
||||
log_assert(port);
|
||||
// Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
|
||||
// in order to extract just the combinatorial control logic that feeds the box
|
||||
// (i.e. clock enable, synchronous reset, etc.)
|
||||
replace.insert(std::make_pair(Q,D));
|
||||
// Since `flatten` above would have created wires named "<cell>.Q",
|
||||
// extract the pre-techmap cell name
|
||||
auto pos = Q.wire->name.str().rfind(".");
|
||||
log_assert(pos != std::string::npos);
|
||||
IdString driver = Q.wire->name.substr(0, pos);
|
||||
// And drive the signal that was previously driven by "DFF.Q" (typically
|
||||
// used to implement clock-enable functionality) with the "<cell>.abc9_ff.Q"
|
||||
// wire (which itself is driven by an input port) we inserted above
|
||||
Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
|
||||
log_assert(currQ);
|
||||
holes_module->connect(Q, currQ);
|
||||
continue;
|
||||
}
|
||||
else if (!cell->type.in("$_NOT_", "$_AND_"))
|
||||
log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
|
||||
++it;
|
||||
}
|
||||
|
||||
for (auto &conn : holes_module->connections_) {
|
||||
auto it = replace.find(sigmap(conn.second));
|
||||
if (it != replace.end())
|
||||
conn.second = it->second;
|
||||
}
|
||||
|
||||
// Move into a new (temporary) design so that "clean" will only
|
||||
// operate (and run checks on) this one module
|
||||
RTLIL::Design *holes_design = new RTLIL::Design;
|
||||
module->design->modules_.erase(holes_module->name);
|
||||
holes_design->add(holes_module);
|
||||
Pass::call(holes_design, "opt -purge");
|
||||
|
||||
std::stringstream a_buffer;
|
||||
XAigerWriter writer(holes_module, true /* holes_mode */);
|
||||
writer.write_aiger(a_buffer, false /*ascii_mode*/);
|
||||
delete holes_design;
|
||||
|
||||
f << "a";
|
||||
std::string buffer_str = a_buffer.str();
|
||||
int32_t buffer_size_be = to_big_endian(buffer_str.size());
|
||||
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
|
||||
f.write(buffer_str.data(), buffer_str.size());
|
||||
|
||||
log_pop();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -917,7 +745,8 @@ struct XAigerBackend : public Backend {
|
|||
log("Write the top module (according to the (* top *) attribute or if only one module\n");
|
||||
log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
|
||||
log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
|
||||
log("pseudo-outputs.\n");
|
||||
log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
|
||||
log("module, if it exists.\n");
|
||||
log("\n");
|
||||
log(" -ascii\n");
|
||||
log(" write ASCII version of AIGER format\n");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue