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gatemate: Add test for LUT tree mapping

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Signed-off-by: gatecat <gatecat@ds0.me>
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gatecat 2022-01-10 09:05:01 +00:00 • committed by myrtle
parent 38a24ec5cc
commit 48efc9b75c
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tests/arch/gatemate/luttrees.ys Normal file
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read_verilog luttrees.v
design -save read
hierarchy -top luttrees
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd luttrees # Constrain all select calls below inside the top module
select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D