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add qlf_k6n10f architecture + bram inference
(Copied from QuickLogic Yosys plugin repo)
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13 changed files with 90338 additions and 21 deletions
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techlibs/quicklogic/quicklogic_eqn.cc
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techlibs/quicklogic/quicklogic_eqn.cc
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/*
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* Copyright 2020-2022 F4PGA Authors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct QuicklogicEqnPass : public Pass {
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QuicklogicEqnPass() : Pass("quicklogic_eqn", "Quicklogic: Calculate equations for luts") {}
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void help() override
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{
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log("\n");
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log(" quicklogic_eqn [selection]\n");
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log("\n");
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log("Calculate equations for luts since bitstream generator depends on it.\n");
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log("\n");
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}
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Const init2eqn(Const init, int inputs)
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{
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std::string init_bits = init.as_string();
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const char *names[] = {"I0", "I1", "I2", "I3", "I4"};
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std::string eqn;
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int width = (int)pow(2, inputs);
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for (int i = 0; i < width; i++) {
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if (init_bits[width - 1 - i] == '1') {
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eqn += "(";
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for (int j = 0; j < inputs; j++) {
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if (i & (1 << j))
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eqn += names[j];
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else
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eqn += std::string("~") + names[j];
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if (j != (inputs - 1))
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eqn += "*";
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}
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eqn += ")+";
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}
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}
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if (eqn.empty())
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return Const("0");
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eqn = eqn.substr(0, eqn.length() - 1);
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return Const(eqn);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing Quicklogic_EQN pass (calculate equations for luts).\n");
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extra_args(args, args.size(), design);
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int cnt = 0;
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for (auto module : design->selected_modules()) {
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for (auto cell : module->selected_cells()) {
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if (cell->type == ID(LUT1)) {
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cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 1));
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cnt++;
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}
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if (cell->type == ID(LUT2)) {
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cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 2));
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cnt++;
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}
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if (cell->type == ID(LUT3)) {
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cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 3));
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cnt++;
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}
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if (cell->type == ID(LUT4)) {
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cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 4));
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cnt++;
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}
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if (cell->type == ID(LUT5)) {
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cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 5));
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cnt++;
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}
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}
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}
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log_header(design, "Updated %d of LUT* elements with equation.\n", cnt);
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}
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} QuicklogicEqnPass;
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PRIVATE_NAMESPACE_END
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