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add qlf_k6n10f architecture + bram inference

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(Copied from QuickLogic Yosys plugin repo)
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N. Engelhardt 2023-11-27 09:42:40 +01:00 • committed by Martin Povišer
parent 98769010af
commit 48c1fdc33d
13 changed files with 90338 additions and 21 deletions
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22
techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt Normal file
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@ -0,0 +1,22 @@
ram block $__QLF_TDP36K {
init any;
byte 9;
option "SPLIT" 0 {
abits 15;
widths 1 2 4 9 18 36 per_port;
}
option "SPLIT" 1 {
abits 14;
widths 1 2 4 9 18 per_port;
}
cost 65;
port srsw "A" "B" {
width tied;
clock posedge;
# wen causes read even when ren is low
# map clken = wen || ren
clken;
wrbe_separate;
rdwr old;
}
}