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Added second divider to GP_RINGOSC

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Andrew Zonenberg 2016-04-06 23:10:34 -07:00
parent 1df559c706
commit 48c10d90f4
1 changed files with 13 additions and 8 deletions
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21
techlibs/greenpak4/cells_sim.v
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@ -80,34 +80,39 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
always begin always begin
if(PWRDN) if(PWRDN)
clkout = 0; CLKOUT = 0;
else begin else begin
//half period of 1730 Hz //half period of 1730 Hz
#289017; #289017;
clkout = ~clkout; CLKOUT = ~CLKOUT;
end end
end end
endmodule endmodule
module GP_RINGOSC(input PWRDN, output reg CLKOUT); module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
parameter PWRDN_EN = 0; parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0; parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1; parameter PRE_DIV = 1;
parameter FABRIC_DIV = 1;
initial CLKOUT = 0; initial CLKOUT_PREDIV = 0;
initial CLKOUT_FABRIC = 0;
//output dividers not implemented for simulation //output dividers not implemented for simulation
//auto powerdown not implemented for simulation //auto powerdown not implemented for simulation
always begin always begin
if(PWRDN) if(PWRDN) begin
clkout = 0; CLKOUT_PREDIV = 0;
CLKOUT_FABRIC = 0;
end
else begin else begin
//half period of 27 MHz //half period of 27 MHz
#18.518; #18.518;
clkout = ~clkout; CLKOUT_PREDIV = ~CLKOUT_PREDIV;
CLKOUT_FABRIC = ~CLKOUT_FABRIC;
end end
end end