mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
Write simulation files after simulation is performed
This commit is contained in:
Miodrag Milanovic
parent
2ca69e1b88
commit
48b56a4f7f
1 changed files with 152 additions and 146 deletions
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@ -70,12 +70,7 @@ struct OutputWriter
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{
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OutputWriter(SimWorker *w) { worker = w;};
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virtual ~OutputWriter() {};
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virtual void write_header() = 0;
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virtual void write_step_header(int t) = 0;
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virtual void enter_scope(IdString) {};
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virtual void exit_scope() {};
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virtual void register_signal(Wire *, int) {};
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virtual void write_value(int, Const&) {};
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virtual void write() = 0;
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SimWorker *worker;
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};
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@ -92,6 +87,7 @@ struct SimShared
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SimulationMode sim_mode = SimulationMode::sim;
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bool cycles_set = false;
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std::vector<std::unique_ptr<OutputWriter>> outputfiles;
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std::vector<std::pair<int,std::map<int,Const>>> output_data;
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};
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void zinit(State &v)
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@ -699,27 +695,37 @@ struct SimInstance
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it.second->writeback(wbmods);
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}
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void write_output_header(OutputWriter *writer, int &id)
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void register_signals(int &id)
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{
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writer->enter_scope(name());
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for (auto wire : module->wires())
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{
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if (shared->hide_internal && wire->name[0] == '$')
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continue;
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signal_database[wire] = make_pair(id, Const());
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writer->register_signal(wire, id);
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id++;
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}
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for (auto child : children)
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child.second->write_output_header(writer, id);
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writer->exit_scope();
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child.second->register_signals(id);
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}
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void write_output_step_values()
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void write_output_header(std::function<void(IdString)> enter_scope, std::function<void()> exit_scope, std::function<void(Wire*, int)> register_signal)
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{
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enter_scope(name());
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for (auto signal : signal_database)
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{
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register_signal(signal.first, signal.second.first);
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}
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for (auto child : children)
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child.second->write_output_header(enter_scope, exit_scope, register_signal);
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exit_scope();
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}
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void register_output_step_values(std::map<int,Const> *data)
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{
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for (auto &it : signal_database)
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{
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@ -731,13 +737,11 @@ struct SimInstance
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continue;
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it.second.second = value;
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for(auto& writer : shared->outputfiles)
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writer->write_value(id, value);
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data->emplace(id, value);
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}
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for (auto child : children)
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child.second->write_output_step_values();
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child.second->register_output_step_values(data);
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}
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void setInitState()
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@ -828,20 +832,24 @@ struct SimWorker : SimShared
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delete top;
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}
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void write_output_header()
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void register_signals()
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{
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for(auto& writer : outputfiles)
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writer->write_header();
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int id = 1;
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top->register_signals(id);
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}
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void write_output_step(int t)
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void register_output_step(int t)
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{
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for(auto& writer : outputfiles)
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writer->write_step_header(t);
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top->write_output_step_values();
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std::map<int,Const> data;
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top->register_output_step_values(&data);
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output_data.emplace_back(t, data);
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}
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void write_output_files()
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{
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for(auto& writer : outputfiles)
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writer->write();
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}
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void update()
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{
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@ -882,6 +890,7 @@ struct SimWorker : SimShared
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{
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log_assert(top == nullptr);
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top = new SimInstance(this, scope, topmod);
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register_signals();
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if (debug)
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log("\n===== 0 =====\n");
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@ -896,8 +905,7 @@ struct SimWorker : SimShared
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update();
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write_output_header();
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write_output_step(0);
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register_output_step(0);
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for (int cycle = 0; cycle < numcycles; cycle++)
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{
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@ -909,7 +917,7 @@ struct SimWorker : SimShared
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set_inports(clockn, State::S1);
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update();
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write_output_step(10*cycle + 5);
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register_output_step(10*cycle + 5);
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if (debug)
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log("\n===== %d =====\n", 10*cycle + 10);
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@ -925,10 +933,12 @@ struct SimWorker : SimShared
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}
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update();
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write_output_step(10*cycle + 10);
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register_output_step(10*cycle + 10);
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}
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write_output_step(10*numcycles + 2);
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register_output_step(10*numcycles + 2);
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write_output_files();
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if (writeback) {
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pool<Module*> wbmods;
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@ -945,6 +955,7 @@ struct SimWorker : SimShared
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log_error("Scope must be defined for co-simulation.\n");
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top = new SimInstance(this, scope, topmod);
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register_signals();
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std::vector<fstHandle> fst_clock;
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@ -1036,12 +1047,11 @@ struct SimWorker : SimShared
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if (initial) {
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top->setInitState();
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write_output_header();
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initial = false;
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}
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if (did_something)
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update();
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write_output_step(time);
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register_output_step(time);
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bool status = top->checkSignals();
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if (status)
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@ -1058,6 +1068,8 @@ struct SimWorker : SimShared
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// end of data detected
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}
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write_output_files();
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if (writeback) {
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pool<Module*> wbmods;
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top->writeback(wbmods);
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@ -1098,6 +1110,8 @@ struct SimWorker : SimShared
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std::string status;
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int cycle = 0;
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top = new SimInstance(this, scope, topmod);
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register_signals();
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while (!f.eof())
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{
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std::string line;
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@ -1109,7 +1123,6 @@ struct SimWorker : SimShared
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state = 2;
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}
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if (state==1 && line[0]!='b' && line[0]!='c') {
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write_output_header();
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// was old format but with 1 bit latch
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top->setState(latches, status);
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state = 3;
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@ -1125,7 +1138,6 @@ struct SimWorker : SimShared
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state = 2;
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break;
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case 2:
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write_output_header();
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top->setState(latches, line);
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state = 3;
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break;
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@ -1141,18 +1153,19 @@ struct SimWorker : SimShared
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set_inports(clockn, State::S1);
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}
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update();
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write_output_step(10*cycle);
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register_output_step(10*cycle);
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if (cycle) {
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set_inports(clock, State::S0);
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set_inports(clockn, State::S1);
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update();
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write_output_step(10*cycle + 5);
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register_output_step(10*cycle + 5);
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}
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cycle++;
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break;
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}
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}
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write_output_step(10*cycle);
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register_output_step(10*cycle);
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write_output_files();
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}
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};
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@ -1162,7 +1175,7 @@ struct VCDWriter : public OutputWriter
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vcdfile.open(filename.c_str());
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}
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void write_header() override
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void write() override
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{
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if (!vcdfile.is_open()) return;
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vcdfile << stringf("$version %s $end\n", yosys_version_str);
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@ -1176,46 +1189,33 @@ struct VCDWriter : public OutputWriter
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if (!worker->timescale.empty())
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vcdfile << stringf("$timescale %s $end\n", worker->timescale.c_str());
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int id = 1;
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worker->top->write_output_header(this, id);
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worker->top->write_output_header(
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[this](IdString name) { vcdfile << stringf("$scope module %s $end\n", log_id(name)); },
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[this]() { vcdfile << stringf("$upscope $end\n");},
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[this](Wire *wire, int id) { vcdfile << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire)); }
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);
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vcdfile << stringf("$enddefinitions $end\n");
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}
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void write_step_header(int t) override
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{
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if (!vcdfile.is_open()) return;
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vcdfile << stringf("#%d\n", t);
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}
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void enter_scope(IdString name) override
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{
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vcdfile << stringf("$scope module %s $end\n", log_id(name));
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}
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for(auto& d : worker->output_data)
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{
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vcdfile << stringf("#%d\n", d.first);
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for (auto &data : d.second)
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{
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void exit_scope() override
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{
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vcdfile << stringf("$upscope $end\n");
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}
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void register_signal(Wire *wire, int id) override
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{
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vcdfile << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire));
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}
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void write_value(int id, Const& value) override
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{
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if (!vcdfile.is_open()) return;
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vcdfile << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: vcdfile << "0"; break;
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case State::S1: vcdfile << "1"; break;
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case State::Sx: vcdfile << "x"; break;
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default: vcdfile << "z";
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Const value = data.second;
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vcdfile << "b";
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: vcdfile << "0"; break;
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case State::S1: vcdfile << "1"; break;
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case State::Sx: vcdfile << "x"; break;
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default: vcdfile << "z";
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}
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}
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vcdfile << stringf(" n%d\n", data.first);
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}
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}
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vcdfile << stringf(" n%d\n", id);
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}
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std::ofstream vcdfile;
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@ -1232,7 +1232,7 @@ struct FSTWriter : public OutputWriter
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fstWriterClose(fstfile);
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}
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void write_header() override
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void write() override
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{
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if (!fstfile) return;
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std::time_t t = std::time(nullptr);
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@ -1244,47 +1244,35 @@ struct FSTWriter : public OutputWriter
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fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ);
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fstWriterSetRepackOnClose(fstfile, 1);
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int id = 1;
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worker->top->write_output_header(this, id);
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}
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void write_step_header(int t) override
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{
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if (!fstfile) return;
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fstWriterEmitTimeChange(fstfile, t);
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}
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void enter_scope(IdString name) override
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{
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fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr);
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}
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void exit_scope() override
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{
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fstWriterSetUpscope(fstfile);
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}
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void register_signal(Wire *wire, int id) override
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{
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fstHandle fst_id = fstWriterCreateVar(fstfile, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
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worker->top->write_output_header(
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[this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",log_id(name)).c_str(), nullptr); },
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[this]() { fstWriterSetUpscope(fstfile); },
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[this](Wire *wire, int id) {
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fstHandle fst_id = fstWriterCreateVar(fstfile, FST_VT_VCD_WIRE, FST_VD_IMPLICIT, GetSize(wire),
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stringf("%s%s", wire->name[0] == '$' ? "\\" : "", log_id(wire)).c_str(), 0);
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mapping.emplace(id, fst_id);
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}
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mapping.emplace(id, fst_id);
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}
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);
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void write_value(int id, Const& value) override
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{
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if (!fstfile) return;
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std::stringstream ss;
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: ss << "0"; break;
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case State::S1: ss << "1"; break;
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case State::Sx: ss << "x"; break;
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default: ss << "z";
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for(auto& d : worker->output_data)
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{
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fstWriterEmitTimeChange(fstfile, d.first);
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for (auto &data : d.second)
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{
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Const value = data.second;
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std::stringstream ss;
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for (int i = GetSize(value)-1; i >= 0; i--) {
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switch (value[i]) {
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case State::S0: ss << "0"; break;
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case State::S1: ss << "1"; break;
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case State::Sx: ss << "x"; break;
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default: ss << "z";
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}
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}
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fstWriterEmitValueChange(fstfile, mapping[data.first], ss.str().c_str());
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}
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}
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fstWriterEmitValueChange(fstfile, mapping[id], ss.str().c_str());
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}
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struct fstContext *fstfile = nullptr;
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@ -1302,7 +1290,7 @@ struct AIWWriter : public OutputWriter
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aiwfile << '.' << '\n';
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}
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void write_header() override
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void write() override
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{
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if (!aiwfile.is_open()) return;
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std::ifstream mf(worker->map_filename);
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@ -1326,50 +1314,68 @@ struct AIWWriter : public OutputWriter
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}
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}
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for (int i = 0;; i++)
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{
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if (aiw_latches.count(i)) {
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auto v = worker->top->get_state(aiw_latches.at(i).first);
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if (v == State::S1)
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aiwfile << (aiw_latches.at(i).second ? '0' : '1');
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else
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aiwfile << (aiw_latches.at(i).second ? '1' : '0');
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continue;
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}
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aiwfile << '\n';
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break;
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}
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}
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worker->top->write_output_header(
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[](IdString) {},
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[]() {},
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[this](Wire *wire, int id) { mapping[wire] = id; }
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);
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void write_step_header(int) override
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{
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if (!aiwfile.is_open()) return;
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for (int i = 0;; i++)
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std::map<int, Yosys::RTLIL::Const> current;
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bool first = true;
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for(auto& d : worker->output_data)
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{
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if (aiw_inputs.count(i)) {
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auto v = worker->top->get_state(aiw_inputs.at(i));
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if (v == State::S1)
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aiwfile << '1';
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else
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aiwfile << '0';
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continue;
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for (auto &data : d.second)
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{
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current[data.first] = data.second;
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}
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if (aiw_inits.count(i)) {
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auto v = worker->top->get_state(aiw_inits.at(i));
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if (v == State::S1)
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aiwfile << '1';
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else
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aiwfile << '0';
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continue;
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if (first) {
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for (int i = 0;; i++)
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{
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if (aiw_latches.count(i)) {
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SigBit bit = aiw_latches.at(i).first;
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auto v = current[mapping[bit.wire]].bits.at(bit.offset);
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if (v == State::S1)
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aiwfile << (aiw_latches.at(i).second ? '0' : '1');
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else
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aiwfile << (aiw_latches.at(i).second ? '1' : '0');
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continue;
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}
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aiwfile << '\n';
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break;
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}
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first = false;
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}
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aiwfile << '\n';
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break;
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}
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for (int i = 0;; i++)
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{
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if (aiw_inputs.count(i)) {
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SigBit bit = aiw_inputs.at(i);
|
||||
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
|
||||
if (v == State::S1)
|
||||
aiwfile << '1';
|
||||
else
|
||||
aiwfile << '0';
|
||||
continue;
|
||||
}
|
||||
if (aiw_inits.count(i)) {
|
||||
SigBit bit = aiw_inits.at(i);
|
||||
auto v = current[mapping[bit.wire]].bits.at(bit.offset);
|
||||
if (v == State::S1)
|
||||
aiwfile << '1';
|
||||
else
|
||||
aiwfile << '0';
|
||||
continue;
|
||||
}
|
||||
aiwfile << '\n';
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
std::ofstream aiwfile;
|
||||
dict<int, std::pair<SigBit, bool>> aiw_latches;
|
||||
dict<int, SigBit> aiw_inputs, aiw_inits;
|
||||
std::map<Wire*,int> mapping;
|
||||
};
|
||||
|
||||
struct SimPass : public Pass {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue