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End of file fix

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:23:41 +02:00
parent 3ac58b3ac1
commit 48a3dcc02a
304 changed files with 64 additions and 321 deletions
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2
tests/sim/assume_x_first_step.ys
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@ -1,2 +1,2 @@
read_verilog simple_assign.v
sim -r simple_assign.vcd -scope simple_assign
sim -r simple_assign.vcd -scope simple_assign

2
tests/sim/simple_assign.vcd
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@ -10,4 +10,4 @@ b1 n1
b1 n2
#10
b0 n1
b0 n2
b0 n2

2
tests/sim/vcd_var_reference_whitespace.ys
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@ -1,3 +1,3 @@
read_rtlil vector_assign.il
sim -r var_reference_without_whitespace.vcd -scope tb.uut
sim -r var_reference_with_whitespace.vcd -scope tb.uut
sim -r var_reference_with_whitespace.vcd -scope tb.uut