mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-30 04:28:55 +00:00
Code Activity

End of file fix

Browse source
This commit is contained in:
Miodrag Milanovic 2026-06-23 07:23:41 +02:00
parent 3ac58b3ac1
commit 48a3dcc02a
304 changed files with 64 additions and 321 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tests/memlib/generate_mk.py
View file

@ -1588,4 +1588,3 @@ extra = [
"endif",
]
gen_tests_makefile.generate_custom(create_tests, extra)

1
tests/memlib/memlib_lut.txt
View file

@ -25,4 +25,3 @@ ram distributed \RAM_LUT {
clock anyedge;
}
}

1
tests/memlib/memlib_wide_write.v
View file

@ -26,4 +26,3 @@ always @(posedge PORT_A_CLK) begin
end
endmodule