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End of file fix

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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:23:41 +02:00
parent 3ac58b3ac1
commit 48a3dcc02a
304 changed files with 64 additions and 321 deletions
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1
techlibs/intel/common/brams_map_m9k.v
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@ -90,4 +90,3 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
.addressstall_b(1'b0));
endmodule

2
techlibs/intel/cyclone10lp/cells_map.v
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@ -71,5 +71,3 @@ module \$lut (A, Y);
endgenerate
endmodule

2
techlibs/intel/cycloneiv/cells_map.v
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@ -55,5 +55,3 @@ module \$lut (A, Y);
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //

2
techlibs/intel/cycloneiv/cells_sim.v
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@ -295,5 +295,3 @@ module cycloneiv_pll
output icdrclk;
endmodule // cycloneive_pll

2
techlibs/intel/cycloneive/cells_map.v
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@ -71,5 +71,3 @@ module \$lut (A, Y);
endgenerate
endmodule

2
techlibs/intel/max10/cells_map.v
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@ -55,5 +55,3 @@ module \$lut (A, Y);
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //

1
techlibs/intel/max10/dsp_map.v
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@ -70,4 +70,3 @@ module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
.dataout (Y)
);
endmodule