End of file fix

techlibs/achronix/speedster22i/cells_map.v

@@ -70,4 +70,3 @@ module  \$_DFF_P_ (input D, C, output Q);
    DFF _TECHMAP_REPLACE_
      (.q(Q), .d(D), .ck(C));
 endmodule
-

techlibs/achronix/speedster22i/cells_sim.v

@@ -74,6 +74,3 @@ module DFF (output reg q,
      q <= d;
 
 endmodule
-
-
-

techlibs/analogdevices/arith_map.v

@@ -170,4 +170,3 @@ module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO);
 
 	assign X = S;
 endmodule
-

techlibs/analogdevices/ff_map.v

@@ -60,4 +60,3 @@ module  \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
 endmodule
 
 `endif
-

techlibs/analogdevices/lut_map.v

@@ -76,4 +76,3 @@ module \$lut (A, Y);
 endmodule
 
 `endif
-

techlibs/fabulous/arith_map.v

@@ -62,4 +62,3 @@ assign X = AA ^ BB;
 
 endmodule
 `endif
-

techlibs/fabulous/io_map.v

@@ -5,4 +5,3 @@ endmodule
 module \$__FABULOUS_OBUF (output PAD, input I);
 	IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0));
 endmodule
-

techlibs/gatemate/gatemate_foldinv.cc

@@ -216,4 +216,3 @@ struct GatemateFoldInvPass : public Pass {
 } GatemateFoldInvPass;
 
 PRIVATE_NAMESPACE_END
-

techlibs/gowin/adc.v

@@ -257,4 +257,3 @@ module ADCA (
   parameter CSR_OFFSET           = -12'd1180;  // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
 
 endmodule
-

techlibs/gowin/arith_map.v

@@ -64,4 +64,3 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
    end endgenerate
    assign X = AA ^ BB ^ {Y_WIDTH{BI}};
 endmodule
-

techlibs/gowin/cells_sim.v

@@ -2151,5 +2151,3 @@ module EMCU (
 
  );
 endmodule
-
-

techlibs/gowin/cells_xtra.py

@@ -103,4 +103,3 @@ if __name__ == '__main__':
                     with open(f'adc.v', 'r') as fin:
                         for l in fin:
                             fout.write(l);
-

techlibs/gowin/cells_xtra_gw5a.v

@@ -2787,4 +2787,3 @@ module ADCA (
   parameter CSR_OFFSET           = -12'd1180;  // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
 
 endmodule
-

techlibs/ice40/arith_map.v

@@ -72,4 +72,3 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 
 	assign X = AA ^ BB;
 endmodule
-

techlibs/ice40/tests/test_bram.sh

@@ -16,4 +16,3 @@ for dbits in 2 4 8 16 24 32; do
 	if grep -H ERROR ${id}_tb.txt; then false; fi
 done; done
 echo OK
-

techlibs/intel/common/brams_map_m9k.v

@@ -90,4 +90,3 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
                                       .addressstall_b(1'b0));
 
 endmodule
-

techlibs/intel/cyclone10lp/cells_map.v

@@ -71,5 +71,3 @@ module \$lut (A, Y);
    endgenerate
 
 endmodule
-
-

techlibs/intel/cycloneiv/cells_map.v

@@ -55,5 +55,3 @@ module \$lut (A, Y);
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
 endmodule //
-
-

techlibs/intel/cycloneiv/cells_sim.v

@@ -295,5 +295,3 @@ module cycloneiv_pll
    output                                   icdrclk;
 
 endmodule // cycloneive_pll
-
-

techlibs/intel/cycloneive/cells_map.v

@@ -71,5 +71,3 @@ module \$lut (A, Y);
    endgenerate
 
 endmodule
-
-

techlibs/intel/max10/cells_map.v

@@ -55,5 +55,3 @@ module \$lut (A, Y);
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
 endmodule //
-
-

techlibs/intel/max10/dsp_map.v

@@ -70,4 +70,3 @@ module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
 		.dataout (Y)
 	);
 endmodule
-

techlibs/intel_alm/common/lutram_mlab.txt

@@ -15,4 +15,4 @@ endbram
 match MISTRAL_MLAB
     min efficiency 5
     make_outreg
-endmatch
+endmatch

techlibs/intel_alm/common/misc_sim.v

@@ -18,4 +18,4 @@ module MISTRAL_CLKBUF (
 	(* clkbuf_driver *) output Q
 );
 	assign Q = A;
-endmodule
+endmodule

techlibs/lattice/cells_bb_ecp5.v

@@ -2030,4 +2030,3 @@ module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_
     input D_REFCLKI;
     output D_FFS_PLOL;
 endmodule
-

techlibs/lattice/cells_bb_nexus.v

@@ -10589,4 +10589,3 @@ module PCLKDIVSP(CLKIN, CLKOUT, LSRPDIV);
     output CLKOUT;
     input LSRPDIV;
 endmodule
-

techlibs/lattice/cells_bb_xo2.v

@@ -579,4 +579,3 @@ endmodule
 module TSALL(TSALL);
     input TSALL;
 endmodule
-

techlibs/lattice/cells_bb_xo3.v

@@ -579,4 +579,3 @@ endmodule
 module TSALL(TSALL);
     input TSALL;
 endmodule
-

techlibs/lattice/cells_bb_xo3d.v

@@ -580,4 +580,3 @@ endmodule
 module TSALL(TSALL);
     input TSALL;
 endmodule
-

techlibs/lattice/lattice_dsp_nexus.cc

@@ -33,4 +33,4 @@ struct LatticeDspNexusPass : public Pass {
 	}
 } LatticeDspNexusPass;
 
-PRIVATE_NAMESPACE_END
+PRIVATE_NAMESPACE_END

techlibs/lattice/lattice_dsp_nexus.pmg

@@ -205,4 +205,4 @@ code
 	}
 
 	accept;
-endcode
+endcode

techlibs/microchip/arith_map.v

@@ -102,4 +102,3 @@ module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
 		);
 	end endgenerate
 endmodule
-

techlibs/microchip/brams_defs.vh

@@ -66,4 +66,4 @@ function [63:0] slice_init_uSRAM;
 	integer i;
 	for (i = 0; i < 64; i = i + 1)
 		slice_init_uSRAM[i] = INIT[(slice_idx * 64 + i)];
-endfunction
+endfunction

techlibs/microchip/cells_map.v

@@ -101,4 +101,3 @@ module \$lut (A, Y);
 	endgenerate
 endmodule
 `endif
-

techlibs/microchip/cells_sim.v

@@ -716,4 +716,4 @@ parameter INIT9 = 64'h0;
 parameter INIT10 = 64'h0;
 parameter INIT11 = 64'h0;
 
-endmodule
+endmodule

techlibs/microchip/microchip_dsp_cascade.pmg

@@ -233,4 +233,4 @@ finally
 	}
 		
 
-endcode
+endcode

techlibs/microchip/uSRAM_map.v

@@ -123,4 +123,3 @@ RAM64x12 #(
 );
 
 endmodule
-

techlibs/nanoxplore/brams.txt

@@ -47,4 +47,4 @@ ram block $__NX_RAM_ {
 		rdwr no_change;
 		rdinit none;
 	}
-}
+}

techlibs/nanoxplore/cells_bb_l.v

@@ -2153,4 +2153,3 @@ module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2,
     parameter sel_clkw_rx1 = 2'b00;
     parameter sel_clkw_rx2 = 2'b00;
 endmodule
-

techlibs/nanoxplore/cells_bb_m.v

@@ -1524,4 +1524,3 @@ module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG,
     parameter data_size = 5;
     parameter location = "";
 endmodule
-

techlibs/nanoxplore/cells_wrap.v

@@ -198,4 +198,3 @@ module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS
   );
 
 endmodule
-

techlibs/nanoxplore/rf_rams_map_u.v

@@ -342,4 +342,4 @@ module $__NX_XRFB_2R_1W_ (
     .WE(PORT_W_WR_EN),
     .WEA(1'b0)
   );
-endmodule
+endmodule

techlibs/quicklogic/ql_bram_types.cc

@@ -162,4 +162,4 @@ struct QlBramTypesPass : public Pass {
 
 } QlBramMergePass;
 
-PRIVATE_NAMESPACE_END
+PRIVATE_NAMESPACE_END

techlibs/quicklogic/qlf_k6n10f/arith_map.v

@@ -96,4 +96,3 @@ module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
 
 	assign X = S;
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/brams_map.v

@@ -4285,4 +4285,4 @@ module BRAM2x18_AFIFO (
 		.FLUSH2_i(Async_Flush2)
 	);
 
-endmodule
+endmodule

techlibs/quicklogic/qlf_k6n10f/brams_sim.v

@@ -10946,4 +10946,4 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split (
 	endspecify
 `endif
 
-endmodule
+endmodule

techlibs/quicklogic/qlf_k6n10f/cells_sim.v

@@ -372,4 +372,3 @@ module latchnsre (
 		endspecify
 
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v

@@ -262,4 +262,3 @@ module dsp_t1_10x9x32_cfg_params (
     assign dly_b_o = dly_b_o[8:0];
 
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/ffs_map.v

@@ -130,4 +130,3 @@ module \$__SHREG_DFF_P_ (D, Q, C);
    endgenerate
 
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v

@@ -480,4 +480,4 @@ TDP36K #(
 	.FLUSH2_i(1'b0)
 );
 
-endmodule
+endmodule

techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v

@@ -61,4 +61,3 @@ module sram1024x18 (
 	end
 
 endmodule
-

techlibs/sf2/arith_map.v

@@ -66,4 +66,3 @@ module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
 		);
 	end endgenerate
 endmodule
-

techlibs/xilinx/arith_map.v

@@ -199,4 +199,3 @@ end else begin
 
 end endgenerate
 endmodule
-

techlibs/xilinx/brams_xcu_map.v

@@ -222,4 +222,3 @@ end
 endgenerate
 
 endmodule
-

techlibs/xilinx/cells_xtra.v

@@ -34826,4 +34826,3 @@ module FE(DEBUG_DOUT, DEBUG_PHASE, INTERRUPT, M_AXIS_DOUT_TDATA, M_AXIS_DOUT_TLA
     input [31:0] S_AXI_WDATA;
     input S_AXI_WVALID;
 endmodule
-

techlibs/xilinx/ff_map.v

@@ -117,4 +117,3 @@ module  \$_DLATCH_PPP_ (input E, S, R, D, output Q);
 endmodule
 
 `endif
-

techlibs/xilinx/lut_map.v

@@ -98,4 +98,3 @@ module \$lut (A, Y);
 endmodule
 
 `endif
-

techlibs/xilinx/tests/bram1.sh

@@ -61,4 +61,3 @@ grep -h 'Mapping to bram type' bram1_*/synth.log | sort | uniq -c
 
 echo "Cleaning up..."
 rm -rf bram1_cmp bram1.mk bram1_[0-9]*/
-

techlibs/xilinx/tests/bram2.sh

@@ -5,4 +5,3 @@ unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
 ../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v
 iverilog -T typ -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
 vvp -N bram2_tb
-

techlibs/xilinx/xc3s_mult_map.v

@@ -11,4 +11,3 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 		.P(Y)
 	);
 endmodule
-

techlibs/xilinx/xc3sda_dsp_map.v

@@ -31,4 +31,3 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-

techlibs/xilinx/xc5v_dsp_map.v

@@ -42,4 +42,3 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-

techlibs/xilinx/xc6s_dsp_map.v

@@ -31,5 +31,3 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-
-

techlibs/xilinx/xcu_dsp_map.v

@@ -48,4 +48,3 @@ module \$__MUL27X18 (input [26:0] A, input [17:0] B, output [44:0] Y);
 	);
 	assign Y = P_48;
 endmodule
-

techlibs/xilinx/xilinx_dffopt.cc

@@ -365,4 +365,3 @@ unmap:
 } XilinxDffOptPass;
 
 PRIVATE_NAMESPACE_END
-