End of file fix

examples/cmos/README

@@ -10,4 +10,3 @@ Each test bench can be run separately by either running:
 
 The later case also includes pure verilog simulation using the iverilog
 and gtkwave for comparison.
-

examples/cmos/cmos_cells.sp

@@ -36,4 +36,3 @@ X1 nC D t DLATCH
 X2 C t Q DLATCH
 X3 C nC NOT
 .ENDS DFF
-

examples/cmos/cmos_cells.v

@@ -41,4 +41,3 @@ always @(posedge C, posedge S, posedge R)
 	else
 		Q <= D;
 endmodule
-

examples/cmos/cmos_cells_digital.sp

@@ -28,4 +28,3 @@ Alatch D E null null Q nQ latch1
 .model dff1 d_dff
 Adff D C null null Q nQ dff1
 .ENDS DFF
-

examples/cmos/counter_digital.ys

@@ -13,4 +13,3 @@ abc -liberty cmos_cells.lib;;
 
 write_verilog synth.v
 write_spice -neg 0s -pos 1s synth.sp
-

examples/cmos/testbench.sh

@@ -4,4 +4,3 @@ set -ex
 
 ../../yosys counter.ys
 ngspice testbench.sp
-

examples/cmos/testbench_digital.sh

@@ -12,4 +12,3 @@ iverilog -o counter_tb counter.v counter_tb.v
 
 # requires ngspice with xspice support enabled:
 ngspice testbench_digital.sp
-