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Miodrag Milanovic 2026-06-23 07:23:41 +02:00
parent 3ac58b3ac1
commit 48a3dcc02a
304 changed files with 64 additions and 321 deletions
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examples/basys3/example.xdc
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@ -21,4 +21,3 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]