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This commit is contained in:
Miodrag Milanovic 2026-06-23 07:23:41 +02:00
parent 3ac58b3ac1
commit 48a3dcc02a
304 changed files with 64 additions and 321 deletions
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1
examples/basys3/README
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@ -16,4 +16,3 @@ Programming board:
All of the above:
bash run.sh

1
examples/basys3/example.xdc
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@ -21,4 +21,3 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

1
examples/cmos/README
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@ -10,4 +10,3 @@ Each test bench can be run separately by either running:
The later case also includes pure verilog simulation using the iverilog
and gtkwave for comparison.

1
examples/cmos/cmos_cells.sp
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@ -36,4 +36,3 @@ X1 nC D t DLATCH
X2 C t Q DLATCH
X3 C nC NOT
.ENDS DFF

1
examples/cmos/cmos_cells.v
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@ -41,4 +41,3 @@ always @(posedge C, posedge S, posedge R)
else
Q <= D;
endmodule

1
examples/cmos/cmos_cells_digital.sp
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@ -28,4 +28,3 @@ Alatch D E null null Q nQ latch1
.model dff1 d_dff
Adff D C null null Q nQ dff1
.ENDS DFF

1
examples/cmos/counter_digital.ys
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@ -13,4 +13,3 @@ abc -liberty cmos_cells.lib;;
write_verilog synth.v
write_spice -neg 0s -pos 1s synth.sp

1
examples/cmos/testbench.sh
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@ -4,4 +4,3 @@ set -ex
../../yosys counter.ys
ngspice testbench.sp

1
examples/cmos/testbench_digital.sh
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@ -12,4 +12,3 @@ iverilog -o counter_tb counter.v counter_tb.v
# requires ngspice with xspice support enabled:
ngspice testbench_digital.sp

1
examples/cxx-api/demomain.cc
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@ -19,4 +19,3 @@ int main()
Yosys::yosys_shutdown();
return 0;
}

1
examples/gowin/README
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@ -14,4 +14,3 @@ gowinTool_linux directory
3.) edit gowinTool_linux/bin/gwlicense.ini. Set lic="..." to
the full path to the license file.

2
examples/gowin/demo.cst
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@ -7,4 +7,4 @@ IO_LOC "leds[3]" 82;
IO_LOC "leds[4]" 83;
IO_LOC "leds[5]" 84;
IO_LOC "leds[6]" 85;
IO_LOC "leds[7]" 86;
IO_LOC "leds[7]" 86;

2
examples/intel/DE2i-150/quartus_compile/de2i.qsf
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@ -1096,4 +1096,4 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

1
examples/intel/MAX10/runme_postsynth
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@ -2,4 +2,3 @@
iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
vvp -N verif_post

1
examples/intel/asicworld_lfsr/runme_postsynth
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@ -2,4 +2,3 @@
iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v)
vvp -N verif_post

2
examples/intel/asicworld_lfsr/runme_presynth
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@ -2,4 +2,4 @@
iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\
vvp -N presynth
vvp -N presynth

1
examples/osu035/Makefile
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@ -10,4 +10,3 @@ osu035_stdcells.lib:
clean:
rm -f osu035_stdcells.lib
rm -f example.yslog example.edif

1
examples/smtbmc/Makefile
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@ -74,4 +74,3 @@ clean:
rm -f glift_mux.ys
.PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 clean

1
examples/smtbmc/demo9.v
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@ -10,4 +10,3 @@ module demo9;
cover(1);
end
endmodule